Commit e5ae728d authored by Komal Bajaj's avatar Komal Bajaj Committed by Wentao Guan
Browse files

EDAC/qcom: Correct interrupt enable register configuration 

stable inclusion
from stable-v6.6.80
commit ae2661f0793bb70dc5b91af3de56ccd235e285d5
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBXANC

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=ae2661f0793bb70dc5b91af3de56ccd235e285d5



--------------------------------

commit c158647c107358bf1be579f98e4bb705c1953292 upstream.

The previous implementation incorrectly configured the cmn_interrupt_2_enable
register for interrupt handling. Using cmn_interrupt_2_enable to configure
Tag, Data RAM ECC interrupts would lead to issues like double handling of the
interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured
for interrupts which needs to be handled by EL3.

EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to configure
Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable.

Fixes: 27450653 ("drivers: edac: Add EDAC driver support for QCOM SoCs")
Signed-off-by: default avatarKomal Bajaj <quic_kbajaj@quicinc.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/20241119064608.12326-1-quic_kbajaj@quicinc.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit ae2661f0793bb70dc5b91af3de56ccd235e285d5)
Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
parent 5ca8de78

drivers/edac/qcom_edac.c

+2 −2
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b 
	 * Configure interrupt enable registers such that Tag, Data RAM related

	 * interrupts are propagated to interrupt controller for servicing

	 */

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,

				 TRP0_INTERRUPT_ENABLE,

				 TRP0_INTERRUPT_ENABLE);

	if (ret)
@@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b 
	if (ret)

		return ret;



	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable,

	ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable,

				 DRP0_INTERRUPT_ENABLE,

				 DRP0_INTERRUPT_ENABLE);

	if (ret)