Commit e59418a4 authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo
Browse files

arm64: dts: imx8m{m,n}-venice-gw7902: add gpio pins for new board revision 



Add gpio pins present on new board revision:
 * LTE modem support (imx8mm-gw7902 only)
  - lte_pwr#
  - lte_rst
  - lte_int
 * M2 power enable
  - m2_pwr_en
 * off-board 4.0V supply
  - vdd_4p0_en

Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent eff6b33c

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

+8 −4
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ 


&gpio1 {

	gpio-line-names = "", "", "", "", "", "", "", "",

		"", "", "", "", "", "m2_reset", "", "m2_wdis#",

		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",

		"", "", "", "", "", "", "", "",

		"", "", "", "", "", "", "", "";

};
@@ -283,7 +283,8 @@ 
&gpio4 {

	gpio-line-names = "", "", "", "", "", "", "", "",

		"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",

		"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",

		"lte_pwr#", "lte_rst", "lte_int", "",

		"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",

		"", "uart1_term", "uart1_half", "app_gpio2",

		"mipi_gpio1", "", "", "";

};
@@ -750,14 +751,19 @@ 
	pinctrl_hog: hoggrp {

		fsl,pins = <

			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */

			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */

			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */

			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */

			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */

			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x40000041 /* LTE_INT */

			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17       0x40000041 /* LTE_RST# */

			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x40000041 /* LTE_PWR */

			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */

			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */

			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */

			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */

			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */

			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */

			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */

			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */

			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
@@ -791,8 +797,6 @@ 
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f

			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */

			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */

			MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x141

			MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT	0x141

		>;

	};

arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts

+4 −4
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ 


&gpio1 {

	gpio-line-names = "", "", "", "", "", "", "", "",

		"", "", "", "", "", "m2_reset", "", "m2_wdis#",

		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",

		"", "", "", "", "", "", "", "",

		"", "", "", "", "", "", "", "";

};
@@ -278,7 +278,7 @@ 
&gpio4 {

	gpio-line-names = "", "", "", "", "", "", "", "",

		"", "", "", "", "", "", "", "",

		"", "", "", "", "", "app_gpio1", "", "uart1_rs485",

		"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",

		"", "uart1_term", "uart1_half", "app_gpio2",

		"mipi_gpio1", "", "", "";

};
@@ -701,10 +701,12 @@ 
	pinctrl_hog: hoggrp {

		fsl,pins = <

			MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */

			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */

			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */

			MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */

			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */

			MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */

			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */

			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */

			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */

			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
@@ -738,8 +740,6 @@ 
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f

			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */

			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */

			MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x141

			MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT	0x141

		>;

	};