Commit e58bd49d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips-fixes-5.17_4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Thomas Bogendoerfer:

 - Fix memory detection for MT7621 devices

 - Fix setnocoherentio kernel option

 - Fix warning when CONFIG_SCHED_CORE is enabled

* tag 'mips-fixes-5.17_4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: ralink: mt7621: use bitwise NOT instead of logical
  mips: setup: fix setnocoherentio() boolean setting
  MIPS: smp: fill in sibling and core maps earlier
  MIPS: ralink: mt7621: do memory detection on KSEG1
parents 4d5ae234 5d896570

arch/mips/kernel/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -803,7 +803,7 @@ early_param("coherentio", setcoherentio); 


static int __init setnocoherentio(char *str)

{

	dma_default_coherent = true;

	dma_default_coherent = false;

	pr_info("Software DMA cache coherency (command line)\n");

	return 0;

}

arch/mips/kernel/smp.c

+3 −3
Original line number Diff line number Diff line
@@ -351,6 +351,9 @@ asmlinkage void start_secondary(void) 
	cpu = smp_processor_id();

	cpu_data[cpu].udelay_val = loops_per_jiffy;



	set_cpu_sibling_map(cpu);

	set_cpu_core_map(cpu);



	cpumask_set_cpu(cpu, &cpu_coherent_mask);

	notify_cpu_starting(cpu);
@@ -362,9 +365,6 @@ asmlinkage void start_secondary(void) 
	/* The CPU is running and counters synchronised, now mark it online */

	set_cpu_online(cpu, true);



	set_cpu_sibling_map(cpu);

	set_cpu_core_map(cpu);



	calculate_cpu_foreign_map();



	/*

arch/mips/ralink/mt7621.c

+23 −13
Original line number Diff line number Diff line
@@ -22,7 +22,9 @@ 


#include "common.h"



static void *detect_magic __initdata = detect_memory_region;

#define MT7621_MEM_TEST_PATTERN         0xaa5555aa



static u32 detect_magic __initdata;



int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)

{
@@ -58,24 +60,32 @@ phys_addr_t mips_cpc_default_phys_base(void) 
	panic("Cannot detect cpc address");

}



static bool __init mt7621_addr_wraparound_test(phys_addr_t size)

{

	void *dm = (void *)KSEG1ADDR(&detect_magic);



	if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)

		return true;

	__raw_writel(MT7621_MEM_TEST_PATTERN, dm);

	if (__raw_readl(dm) != __raw_readl(dm + size))

		return false;

	__raw_writel(~MT7621_MEM_TEST_PATTERN, dm);

	return __raw_readl(dm) == __raw_readl(dm + size);

}



static void __init mt7621_memory_detect(void)

{

	void *dm = &detect_magic;

	phys_addr_t size;



	for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {

		if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))

			break;

	for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {

		if (mt7621_addr_wraparound_test(size)) {

			memblock_add(MT7621_LOWMEM_BASE, size);

			return;

		}

	}



	if ((size == 256 * SZ_1M) &&

	    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&

	    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {

	memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);

	memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);

	} else {

		memblock_add(MT7621_LOWMEM_BASE, size);

	}

}



void __init ralink_of_remap(void)