Unverified Commit e58177e3 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!5149 net: hns3: add support some customized exception handling interfaces 

Merge Pull Request from: @svishen 
 
This pr add support some customized exception handling interfaces.

Hao Chen (2):
  net: hns3: add support to get/set 1d torus param
  net: hns3: add support modified tx timeout

Jian Shen (2):
  net: hns3: add extend interface support for read and write phy
    register
  net: hns3: add input parameters checking

Jie Wang (1):
  net: hns3: add support PF provides customized interfaces to detect
    port faults.

shaojijie (13):
  net: hns3: add support customized exception handling interfaces
  net: hns3: add supports pfc storm detection and suppression
  net: hns3: add supports fast reporting of faulty nodes
  net: hns3: add support clear mac statistics
  net: hns3: add support configuring function-level interrupt affinity
  net: hns3: add support query port ext information
  net: hns3: add support query the presence of optical module
  net: hns3: add supports configure optical module enable
  net: hns3: add support config and query serdes lane status
  net: hns3: add support disable nic clock
  net: hns3: support set pfc pause trans time
  net: hns3: add support detect port wire type
  net: hns3: add support set led

wangpeiyang (1):
  net: hns3: add support set mac state

issue：
https://gitee.com/openeuler/kernel/issues/I97T47?from=project-issue
 
 
Link:https://gitee.com/openeuler/kernel/pulls/5149

 

Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents 0f49d2e3 5f01b084

drivers/net/ethernet/hisilicon/hns3/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ obj-$(CONFIG_HNS3) += hnae3.o 


obj-$(CONFIG_HNS3_ENET) += hns3.o

hns3-objs = hns3_enet.o hns3_ethtool.o hns3_debugfs.o

hns3-objs += hns3_ext.o



hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o
@@ -24,6 +25,6 @@ obj-$(CONFIG_HNS3_HCLGE) += hclge.o 
hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o hns3pf/hclge_regs.o \

		hns3pf/hclge_mbx.o hns3pf/hclge_err.o  hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o \

		hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o



hclge-objs += hns3pf/hclge_ext.o



hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+7 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define HNAE3_DEVICE_VERSION_V1   0x00020

#define HNAE3_DEVICE_VERSION_V2   0x00021

#define HNAE3_DEVICE_VERSION_V3   0x00030

#define HNAE3_DEVICE_VERSION_V4   0x00032



#define HNAE3_PCI_REVISION_BIT_SIZE		8
@@ -104,6 +105,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_WOL_B,

	HNAE3_DEV_SUPPORT_TM_FLUSH_B,

	HNAE3_DEV_SUPPORT_VF_FAULT_B,

	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -181,6 +183,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_vf_fault_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)



#define hnae3_ae_dev_notify_pkt_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};
@@ -782,6 +787,8 @@ struct hnae3_ae_ops { 
			struct ethtool_wolinfo *wol);

	int (*set_wol)(struct hnae3_handle *handle,

		       struct ethtool_wolinfo *wol);

	int (*priv_ops)(struct hnae3_handle *handle, int opcode,

			void *data, size_t length);

};



struct hnae3_dcb_ops {

drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h

0 → 100644
+121 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

// Copyright (c) 2023 Hisilicon Limited.



#ifndef __HNAE3_EXT_H

#define __HNAE3_EXT_H



enum hnae3_event_type_custom {

	HNAE3_VF_RESET_CUSTOM,

	HNAE3_VF_FUNC_RESET_CUSTOM,

	HNAE3_VF_PF_FUNC_RESET_CUSTOM,

	HNAE3_VF_FULL_RESET_CUSTOM,

	HNAE3_FLR_RESET_CUSTOM,

	HNAE3_FUNC_RESET_CUSTOM,

	HNAE3_GLOBAL_RESET_CUSTOM,

	HNAE3_IMP_RESET_CUSTOM,

	HNAE3_UNKNOWN_RESET_CUSTOM,

	HNAE3_NONE_RESET_CUSTOM,

	HNAE3_PORT_FAULT,

	HNAE3_RESET_DONE_CUSTOM,

	HNAE3_FUNC_RESET_FAIL_CUSTOM,

	HNAE3_GLOBAL_RESET_FAIL_CUSTOM,

	HNAE3_IMP_RESET_FAIL_CUSTOM,

	HNAE3_PPU_POISON_CUSTOM,

	HNAE3_IMP_RD_POISON_CUSTOM,

	HNAE3_ROCEE_AXI_RESP_CUSTOM,

	HNAE3_INVALID_EVENT_CUSTOM,

};



enum hnae3_ext_opcode {

	HNAE3_EXT_OPC_RESET,

	HNAE3_EXT_OPC_EVENT_CALLBACK,

	HNAE3_EXT_OPC_GET_PFC_STORM_PARA,

	HNAE3_EXT_OPC_SET_PFC_STORM_PARA,

	HNAE3_EXT_OPC_SET_NOTIFY_PARAM,

	HNAE3_EXT_OPC_SET_NOTIFY_START,

	HNAE3_EXT_OPC_SET_TORUS_PARAM,

	HNAE3_EXT_OPC_GET_TORUS_PARAM,

	HNAE3_EXT_OPC_CLEAN_STATS64,

	HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,

	HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,

	HNAE3_EXT_OPC_GET_PORT_NUM,

	HNAE3_EXT_OPC_GET_PRESENT,

	HNAE3_EXT_OPC_SET_SFP_STATE,

	HNAE3_EXT_OPC_DISABLE_LANE,

	HNAE3_EXT_OPC_GET_LANE_STATUS,

	HNAE3_EXT_OPC_DISABLE_CLOCK,

	HNAE3_EXT_OPC_SET_PFC_TIME,

	HNAE3_EXT_OPC_GET_HILINK_REF_LOS,

	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,

	HNAE3_EXT_OPC_GET_PORT_TYPE,

	HNAE3_EXT_OPC_SET_MAC_STATE,

	HNAE3_EXT_OPC_SET_LED,

	HNAE3_EXT_OPC_GET_LED_SIGNAL,

	HNAE3_EXT_OPC_GET_PHY_REG,

	HNAE3_EXT_OPC_SET_PHY_REG,

};



struct hnae3_led_state_para {

	u32 type;

	u32 status;

};



struct hnae3_phy_para {

	u32 page_select_addr;

	u32 reg_addr;

	u16 page;

	u16 data;

};



struct hnae3_lamp_signal {

	u8 error;

	u8 locate;

	u8 activity;

};



struct hnae3_pfc_storm_para {

	u32 dir;

	u32 enable;

	u32 period_ms;

	u32 times;

	u32 recovery_period_ms;

};



enum hnae3_port_fault_type {

	HNAE3_FAULT_TYPE_CDR_FLASH,

	HNAE3_FAULT_TYPE_9545_ERR,

	HNAE3_FAULT_TYPE_CDR_CORE,

	HNAE3_FAULT_TYPE_HILINK_REF_LOS,

	HNAE3_FAULT_TYPE_INVALID

};



struct hnae3_port_fault {

	u32 fault_type;

	u32 fault_status;

};



struct hnae3_notify_pkt_param {

	u32 ipg;     /* inter-packet gap of sending, the unit is one cycle of clock */

	u16 num;     /* packet number of sending */

	u8 enable;   /* send enable, 0=Disable, 1=Enable */

	u8 init;     /* initialization flag, product does not need to set value */

	u8 data[64]; /* note packet data */

};



struct hnae3_torus_param {

	u32 enable;       /* 1d torus mode enable */

	u32 mac_id;       /* export mac id of port */

	u8 is_node0;      /* if current node is node0 */

};



struct hane3_port_ext_id_info {

	u32 chip_id;

	u32 mac_id;

	u32 io_die_id;

};



struct hane3_port_ext_num_info {

	u32 chip_num;

	u32 io_die_num;

};

#endif

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},

	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},

	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},

	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+18 −0
Original line number Diff line number Diff line
@@ -310,6 +310,23 @@ enum hclge_opcode_type { 


	/* Query link diagnosis info command */

	HCLGE_OPC_QUERY_LINK_DIAGNOSIS	= 0x702A,



	/* EXT command */

	HCLGE_OPC_CONFIG_NIC_CLOCK = 0x0060,

	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,

	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,

	HCLGE_OPC_SET_NOTIFY_PKT = 0x180A,

	HCLGE_OPC_CONFIG_1D_TORUS = 0x2300,

	HCLGE_OPC_CHIP_ID_GET = 0x7003,

	HCLGE_OPC_GET_CHIP_NUM = 0x7005,

	HCLGE_OPC_GET_PORT_NUM = 0x7006,

	HCLGE_OPC_SET_LED = 0x7007,

	HCLGE_OPC_DISABLE_NET_LANE = 0x7008,

	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,

	HCLGE_OPC_CFG_GET_HILINK_REF_LOS = 0x701B,

	HCLGE_OPC_GET_PORT_FAULT_STATUS = 0x7023,

	HCLGE_OPC_SFP_GET_PRESENT = 0x7101,

	HCLGE_OPC_SFP_SET_STATUS = 0x7102,

};



enum hclge_comm_cmd_return_status {
@@ -352,6 +369,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_VF_FAULT_B = 26,

	HCLGE_COMM_CAP_LANE_NUM_B = 27,

	HCLGE_COMM_CAP_WOL_B = 28,

	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,

	HCLGE_COMM_CAP_TM_FLUSH_B = 31,

};