Commit e52984be authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge tag 'linux-can-fixes-for-5.17-20220124' of... 

Merge tag 'linux-can-fixes-for-5.17-20220124' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can

Marc Kleine-Budde says:

====================
pull-request: can 2022-01-24

The first patch updates the email address of Brian Silverman from his
former employer to his private address.

The next patch fixes DT bindings information for the tcan4x5x SPI CAN
driver.

The following patch targets the m_can driver and fixes the
introduction of FIFO bulk read support.

Another patch for the tcan4x5x driver, which fixes the max register
value for the regmap config.

The last patch for the flexcan driver marks the RX mailbox support for
the MCF5441X as support.

* tag 'linux-can-fixes-for-5.17-20220124' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can:
  can: flexcan: mark RX via mailboxes as supported on MCF5441X
  can: tcan4x5x: regmap: fix max register value
  can: m_can: m_can_fifo_{read,write}: don't read or write from/to FIFO if length is 0
  dt-bindings: can: tcan4x5x: fix mram-cfg RX FIFO config
  mailmap: update email address of Brian Silverman
====================

Link: https://lore.kernel.org/r/20220124175955.3464134-1-mkl@pengutronix.de


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents de8a820d f04aefd4

.mailmap

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> 
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>

Brian Avery <b.avery@hp.com>

Brian King <brking@us.ibm.com>

Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com>

Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>

Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>

Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>

Documentation/devicetree/bindings/net/can/tcan4x5x.txt

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ tcan4x5x: tcan4x5x@0 { 
		#address-cells = <1>;

		#size-cells = <1>;

		spi-max-frequency = <10000000>;

		bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;

		bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;

		interrupt-parent = <&gpio1>;

		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;

		device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;

drivers/net/can/flexcan/flexcan-core.c

+1 −0
Original line number Diff line number Diff line
@@ -296,6 +296,7 @@ static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8); 
static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {

	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |

		FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |

		FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |

		FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,

};

drivers/net/can/flexcan/flexcan.h

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
 * Below is some version info we got:

 *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece-   FD Mode     MB

 *                                Filter? connected?  Passive detection  ption in MB Supported?

 * MCF5441X FlexCAN2  ?               no       yes        no       no       yes           no     16

 * MCF5441X FlexCAN2  ?               no       yes        no       no        no           no     16

 *    MX25  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64

 *    MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no           no     64

 *    MX35  FlexCAN2  03.00.00.00     no        no        no       no        no           no     64

drivers/net/can/m_can/m_can.c

+6 −0
Original line number Diff line number Diff line
@@ -336,6 +336,9 @@ m_can_fifo_read(struct m_can_classdev *cdev, 
	u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +

		offset;



	if (val_count == 0)

		return 0;



	return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);

}
@@ -346,6 +349,9 @@ m_can_fifo_write(struct m_can_classdev *cdev, 
	u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +

		offset;



	if (val_count == 0)

		return 0;



	return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);

}