Commit e5285565 authored by Feifei Xu's avatar Feifei Xu Committed by Alex Deucher
Browse files

drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic. 



SDMA 4_x asics share the same MGCG/MGLS setting.

Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9a65df19

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+4 −15
Original line number Diff line number Diff line
@@ -2222,21 +2222,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle, 
	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_VEGA10:

	case CHIP_VEGA12:

	case CHIP_VEGA20:

	case CHIP_RAVEN:

	case CHIP_ARCTURUS:

	case CHIP_RENOIR:

	sdma_v4_0_update_medium_grain_clock_gating(adev,

			state == AMD_CG_STATE_GATE);

	sdma_v4_0_update_medium_grain_light_sleep(adev,

			state == AMD_CG_STATE_GATE);

		break;

	default:

		break;

	}

	return 0;

}