Commit e5240c35 authored by Arınç ÜNAL's avatar Arınç ÜNAL Committed by Matthias Brugger
Browse files

arm: dts: mt7623: add mt7530 switch to mt7623a.dtsi



The MT7530 switch is included as a part of the multi-chip module on the
MT7623AI SoC. Add it to mt7623a.dtsi and adjust DTs that call mt7623a.dtsi.

Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/r/20230210182505.24597-3-arinc.unal@arinc9.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent f847a3a8
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+22 −65
Original line number Diff line number Diff line
@@ -112,75 +112,32 @@
	status = "okay";
};

&gmac0 {
	status = "okay";
	phy-mode = "trgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
	};
};

&eth {
	status = "okay";

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7530";
			reg = <0>;
			mediatek,mcm;
			resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
			reset-names = "mcm";
			core-supply = <&mt6323_vpa_reg>;
			io-supply = <&mt6323_vemc3v3_reg>;

&switch0 {
	ports {
				#address-cells = <1>;
				#size-cells = <0>;

		port@0 {
					reg = <0>;
			status = "okay";
			label = "lan0";
		};

		port@1 {
					reg = <1>;
			status = "okay";
			label = "lan1";
		};

		port@2 {
					reg = <2>;
			status = "okay";
			label = "lan2";
		};

		port@3 {
					reg = <3>;
			status = "okay";
			label = "lan3";
		};

		port@4 {
					reg = <4>;
			status = "okay";
			label = "wan";
		};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "trgmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};
	};
};

+22 −65
Original line number Diff line number Diff line
@@ -116,75 +116,32 @@
	status = "okay";
};

&gmac0 {
	status = "okay";
	phy-mode = "trgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
	};
};

&eth {
	status = "okay";

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7530";
			reg = <0>;
			mediatek,mcm;
			resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
			reset-names = "mcm";
			core-supply = <&mt6323_vpa_reg>;
			io-supply = <&mt6323_vemc3v3_reg>;

&switch0 {
	ports {
				#address-cells = <1>;
				#size-cells = <0>;

		port@0 {
					reg = <0>;
			status = "okay";
			label = "lan0";
		};

		port@1 {
					reg = <1>;
			status = "okay";
			label = "lan1";
		};

		port@2 {
					reg = <2>;
			status = "okay";
			label = "lan2";
		};

		port@3 {
					reg = <3>;
			status = "okay";
			label = "lan3";
		};

		port@4 {
					reg = <4>;
			status = "okay";
			label = "wan";
		};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "trgmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};
	};
};

+74 −0
Original line number Diff line number Diff line
@@ -17,8 +17,82 @@
	power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>;
};

&gmac0 {
	status = "okay";
	phy-mode = "trgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
		pause;
	};
};

&eth {
	status = "okay";
	power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>;

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch0: switch@0 {
			compatible = "mediatek,mt7530";
			reg = <0>;
			mediatek,mcm;
			resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
			reset-names = "mcm";
			core-supply = <&mt6323_vpa_reg>;
			io-supply = <&mt6323_vemc3v3_reg>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					status = "disabled";
					reg = <0>;
					label = "swp0";
				};

				port@1 {
					status = "disabled";
					reg = <1>;
					label = "swp1";
				};

				port@2 {
					status = "disabled";
					reg = <2>;
					label = "swp2";
				};

				port@3 {
					status = "disabled";
					reg = <3>;
					label = "swp3";
				};

				port@4 {
					status = "disabled";
					reg = <4>;
					label = "swp4";
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "trgmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};
	};
};

&nandc {