Commit e500ba0e authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'omap-for-v5.6/fixes-rc2' into fixes

parents 10dc62d0 00a39c92

arch/arm/boot/dts/am437x-idk-evm.dts

+2 −2
Original line number Diff line number Diff line
@@ -526,11 +526,11 @@ 
	 * Supply voltage supervisor on board will not allow opp50 so

	 * disable it and set opp100 as suspend OPP.

	 */

	opp50@300000000 {

	opp50-300000000 {

		status = "disabled";

	};



	opp100@600000000 {

	opp100-600000000 {

		opp-suspend;

	};

};

arch/arm/boot/dts/dra7-evm.dts

+2 −2
Original line number Diff line number Diff line
@@ -61,10 +61,10 @@ 
		regulator-max-microvolt = <1800000>;

	};



	evm_3v3: fixedregulator-evm3v3 {

	vsys_3v3: fixedregulator-vsys3v3 {

		/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */

		compatible = "regulator-fixed";

		regulator-name = "evm_3v3";

		regulator-name = "vsys_3v3";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		vin-supply = <&evm_12v0>;

arch/arm/boot/dts/dra7-l4.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -3474,6 +3474,7 @@ 
				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;

				clock-names = "fck";

				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;

				ti,timer-pwm;

			};

		};
@@ -3501,6 +3502,7 @@ 
				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;

				clock-names = "fck";

				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;

				ti,timer-pwm;

			};

		};
@@ -3528,6 +3530,7 @@ 
				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;

				clock-names = "fck";

				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;

				ti,timer-pwm;

			};

		};
@@ -3555,6 +3558,7 @@ 
				clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;

				clock-names = "fck";

				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;

				ti,timer-pwm;

			};

		};

arch/arm/boot/dts/dra7xx-clocks.dtsi

+2 −10
Original line number Diff line number Diff line
@@ -796,16 +796,6 @@ 
		clock-div = <1>;

	};



	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;

		ti,bit-shift = <24>;

		reg = <0x0520>;

		assigned-clocks = <&ipu1_gfclk_mux>;

		assigned-clock-parents = <&dpll_core_h22x2_ck>;

	};



	dummy_ck: dummy_ck {

		#clock-cells = <0>;

		compatible = "fixed-clock";
@@ -1564,6 +1554,8 @@ 
			compatible = "ti,clkctrl";

			reg = <0x20 0x4>;

			#clock-cells = <2>;

			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;

			assigned-clock-parents = <&dpll_core_h22x2_ck>;

		};



		ipu_clkctrl: ipu-clkctrl@50 {