Commit e4e64486 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Viresh Kumar
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cpufreq: qcom-cpufreq-hw: Clear dcvs interrupts 



It's noted that dcvs interrupts are not self-clearing, thus an interrupt
handler runs constantly, which leads to a severe regression in runtime.
To fix the problem an explicit write to clear interrupt register is
required, note that on OSM platforms the register may not be present.

Fixes: 275157b3 ("cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support")
Signed-off-by: default avatarVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 1aa24a8f

drivers/cpufreq/qcom-cpufreq-hw.c

+8 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#define CLK_HW_DIV			2

#define LUT_TURBO_IND			1



#define GT_IRQ_STATUS			BIT(2)



#define HZ_PER_KHZ			1000



struct qcom_cpufreq_soc_data {
@@ -32,6 +34,7 @@ struct qcom_cpufreq_soc_data { 
	u32 reg_dcvs_ctrl;

	u32 reg_freq_lut;

	u32 reg_volt_lut;

	u32 reg_intr_clr;

	u32 reg_current_vote;

	u32 reg_perf_state;

	u8 lut_row_size;
@@ -360,6 +363,10 @@ static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data) 
	disable_irq_nosync(c_data->throttle_irq);

	schedule_delayed_work(&c_data->throttle_work, 0);



	if (c_data->soc_data->reg_intr_clr)

		writel_relaxed(GT_IRQ_STATUS,

			       c_data->base + c_data->soc_data->reg_intr_clr);



	return IRQ_HANDLED;

}
@@ -379,6 +386,7 @@ static const struct qcom_cpufreq_soc_data epss_soc_data = { 
	.reg_dcvs_ctrl = 0xb0,

	.reg_freq_lut = 0x100,

	.reg_volt_lut = 0x200,

	.reg_intr_clr = 0x308,

	.reg_perf_state = 0x320,

	.lut_row_size = 4,

};