Commit e4c9200d authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: implement SMU V11 common APIs for retrieving link speed/width 



This will be shared around all SMU V11 asics.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 25c933b1

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+8 −0
Original line number Diff line number Diff line
@@ -264,5 +264,13 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu, 
				  uint32_t *min_value,

				  uint32_t *max_value);



int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);



int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);



int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);



int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);



#endif

#endif

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+2 −7
Original line number Diff line number Diff line
@@ -917,7 +917,6 @@ static int navi10_print_clk_levels(struct smu_context *smu, 
	uint32_t gen_speed, lane_width;

	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;

	struct amdgpu_device *adev = smu->adev;

	PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;

	OverDriveTable_t *od_table =

		(OverDriveTable_t *)table_context->overdrive_table;
@@ -971,12 +970,8 @@ static int navi10_print_clk_levels(struct smu_context *smu, 
		}

		break;

	case SMU_PCIE:

		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &

			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)

			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;

		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &

			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)

			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;

		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);

		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);

		for (i = 0; i < NUM_LINK_LEVELS; i++)

			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,

					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :

drivers/gpu/drm/amd/powerplay/navi10_ppt.h

+0 −3
Original line number Diff line number Diff line
@@ -49,9 +49,6 @@ 


#define NAVI10_VOLTAGE_SCALE (4)



#define smnPCIE_LC_SPEED_CNTL			0x11140290

#define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288



extern void navi10_set_ppt_funcs(struct smu_context *smu);



#endif

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+2 −6
Original line number Diff line number Diff line
@@ -960,12 +960,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 
		}

		break;

	case SMU_PCIE:

		gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &

			     PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)

			>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;

		lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &

			      PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)

			>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;

		gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);

		lane_width = smu_v11_0_get_current_pcie_link_width(smu);

		for (i = 0; i < NUM_LINK_LEVELS; i++)

			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,

					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.h

+0 −3
Original line number Diff line number Diff line
@@ -31,7 +31,4 @@ typedef enum { 


extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);



#define smnPCIE_LC_SPEED_CNTL                   0x11140290

#define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288



#endif