Commit e49c2912 authored by Eric Biggers's avatar Eric Biggers Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sdm630: add ICE registers and clocks 



Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the sdhci-msm host controller on sdm630.  This
allows sdhci-msm to support inline encryption on sdm630.

Signed-off-by: default avatarEric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20210121090140.326380-9-ebiggers@kernel.org


[bjorn: Changed indentation]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 687cc021

arch/arm64/boot/dts/qcom/sdm630.dtsi

+7 −5
Original line number Diff line number Diff line
@@ -808,8 +808,9 @@ 
		sdhc_1: sdhci@c0c4000 {

			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x0c0c4000 0x1000>,

				<0x0c0c5000 0x1000>;

			reg-names = "hc", "cqhci";

			      <0x0c0c5000 0x1000>,

			      <0x0c0c8000 0x8000>;

			reg-names = "hc", "cqhci", "ice";



			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
@@ -817,8 +818,9 @@ 


			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

					<&xo_board>;

			clock-names = "core", "iface", "xo";

				 <&xo_board>,

				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;

			clock-names = "core", "iface", "xo", "ice";



			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;