Commit e49a656b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/fbc: Start passing around intel_fbc



In preparation for multiple FBC instances start passing around
intel_fbc pointers rather than i915 pointers. And once there are
multiple of these we can't rely on container_of() to get back to
the i915, so we toss in a fbc->i915 pointer already.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211104144520.22605-17-ville.syrjala@linux.intel.com


Acked-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent d0618823
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+1 −1
Original line number Diff line number Diff line
@@ -10815,7 +10815,7 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
	destroy_workqueue(i915->flip_wq);
	destroy_workqueue(i915->modeset_wq);

	intel_fbc_cleanup_cfb(i915);
	intel_fbc_cleanup(i915);
}

/* part #3: call after gem init */
+4 −4
Original line number Diff line number Diff line
@@ -52,10 +52,10 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
	mutex_lock(&fbc->lock);

	if (intel_fbc_is_active(dev_priv)) {
	if (intel_fbc_is_active(fbc)) {
		seq_puts(m, "FBC enabled\n");
		seq_printf(m, "Compressing: %s\n",
			   yesno(intel_fbc_is_compressing(dev_priv)));
			   yesno(intel_fbc_is_compressing(fbc)));
	} else {
		seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
	}
@@ -79,7 +79,7 @@ static int i915_fbc_false_color_set(void *data, u64 val)
{
	struct drm_i915_private *dev_priv = data;

	return intel_fbc_set_false_color(dev_priv, val);
	return intel_fbc_set_false_color(&dev_priv->fbc, val);
}

DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops,
@@ -2063,7 +2063,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
			return ret;
	}

	ret = intel_fbc_reset_underrun(dev_priv);
	ret = intel_fbc_reset_underrun(&dev_priv->fbc);
	if (ret)
		return ret;

+185 −194

File changed.

Preview size limit exceeded, changes collapsed.

+7 −7
Original line number Diff line number Diff line
@@ -14,17 +14,19 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_fbc;
struct intel_plane_state;

void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
			   struct intel_atomic_state *state);
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
bool intel_fbc_is_compressing(struct drm_i915_private *dev_priv);
bool intel_fbc_is_active(struct intel_fbc *fbc);
bool intel_fbc_is_compressing(struct intel_fbc *fbc);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
			  struct intel_crtc *crtc);
void intel_fbc_post_update(struct intel_atomic_state *state,
			   struct intel_crtc *crtc);
void intel_fbc_init(struct drm_i915_private *dev_priv);
void intel_fbc_cleanup(struct drm_i915_private *dev_priv);
void intel_fbc_update(struct intel_atomic_state *state,
		      struct intel_crtc *crtc);
void intel_fbc_disable(struct intel_crtc *crtc);
@@ -34,10 +36,8 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
			  enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
int intel_fbc_set_false_color(struct drm_i915_private *i915,
			      bool enable);
void intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc);
int intel_fbc_reset_underrun(struct intel_fbc *fbc);
int intel_fbc_set_false_color(struct intel_fbc *fbc, bool enable);

#endif /* __INTEL_FBC_H__ */
+1 −1
Original line number Diff line number Diff line
@@ -434,7 +434,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
	}

	intel_fbc_handle_fifo_underrun_irq(dev_priv);
	intel_fbc_handle_fifo_underrun_irq(&dev_priv->fbc);
}

/**
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