Commit e43ae8b6 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-riscv-6.6-1' of https://github.com/kvm-riscv/linux into HEAD 

KVM/riscv changes for 6.6

- Zba, Zbs, Zicntr, Zicsr, Zifencei, and Zihpm support for Guest/VM
- Added ONE_REG interface for SATP mode
- Added ONE_REG interface to enable/disable multiple ISA extensions
- Improved error codes returned by ONE_REG interfaces
- Added KVM_GET_REG_LIST ioctl() implementation for KVM RISC-V
- Added get-reg-list selftest for KVM RISC-V
parents 69fd3876 47706939

Documentation/virt/kvm/api.rst

+3 −1
Original line number Diff line number Diff line
@@ -2259,6 +2259,8 @@ Errors: 
  EINVAL   invalid register ID, or no such register or used with VMs in

           protected virtualization mode on s390

  EPERM    (arm64) register access not allowed before vcpu finalization

  EBUSY    (riscv) changing register value not allowed after the vcpu

           has run at least once

  ======   ============================================================



(These error codes are indicative only: do not rely on a specific error
@@ -3499,7 +3501,7 @@ VCPU matching underlying host. 
---------------------



:Capability: basic

:Architectures: arm64, mips

:Architectures: arm64, mips, riscv

:Type: vcpu ioctl

:Parameters: struct kvm_reg_list (in/out)

:Returns: 0 on success; -1 on error

arch/riscv/include/asm/csr.h

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ 
#ifndef CONFIG_64BIT

#define SATP_PPN	_AC(0x003FFFFF, UL)

#define SATP_MODE_32	_AC(0x80000000, UL)

#define SATP_MODE_SHIFT	31

#define SATP_ASID_BITS	9

#define SATP_ASID_SHIFT	22

#define SATP_ASID_MASK	_AC(0x1FF, UL)
@@ -62,6 +63,7 @@ 
#define SATP_MODE_39	_AC(0x8000000000000000, UL)

#define SATP_MODE_48	_AC(0x9000000000000000, UL)

#define SATP_MODE_57	_AC(0xa000000000000000, UL)

#define SATP_MODE_SHIFT	60

#define SATP_ASID_BITS	16

#define SATP_ASID_SHIFT	44

#define SATP_ASID_MASK	_AC(0xFFFF, UL)

arch/riscv/include/asm/kvm_host.h

+9 −0
Original line number Diff line number Diff line
@@ -337,6 +337,15 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 


void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch);



void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu);

unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu);

int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,

				    u64 __user *uindices);

int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,

			   const struct kvm_one_reg *reg);

int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,

			   const struct kvm_one_reg *reg);



int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq);

int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq);

void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu);

arch/riscv/include/asm/kvm_vcpu_vector.h

+2 −4
Original line number Diff line number Diff line
@@ -74,9 +74,7 @@ static inline void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) 
#endif



int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu,

				  const struct kvm_one_reg *reg,

				  unsigned long rtype);

				  const struct kvm_one_reg *reg);

int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu,

				  const struct kvm_one_reg *reg,

				  unsigned long rtype);

				  const struct kvm_one_reg *reg);

#endif

arch/riscv/include/uapi/asm/kvm.h

+16 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ struct kvm_riscv_config { 
	unsigned long marchid;

	unsigned long mimpid;

	unsigned long zicboz_block_size;

	unsigned long satp_mode;

};



/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
@@ -124,6 +125,12 @@ enum KVM_RISCV_ISA_EXT_ID { 
	KVM_RISCV_ISA_EXT_SSAIA,

	KVM_RISCV_ISA_EXT_V,

	KVM_RISCV_ISA_EXT_SVNAPOT,

	KVM_RISCV_ISA_EXT_ZBA,

	KVM_RISCV_ISA_EXT_ZBS,

	KVM_RISCV_ISA_EXT_ZICNTR,

	KVM_RISCV_ISA_EXT_ZICSR,

	KVM_RISCV_ISA_EXT_ZIFENCEI,

	KVM_RISCV_ISA_EXT_ZIHPM,

	KVM_RISCV_ISA_EXT_MAX,

};
@@ -193,6 +200,15 @@ enum KVM_RISCV_SBI_EXT_ID { 


/* ISA Extension registers are mapped as type 7 */

#define KVM_REG_RISCV_ISA_EXT		(0x07 << KVM_REG_RISCV_TYPE_SHIFT)

#define KVM_REG_RISCV_ISA_SINGLE	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)

#define KVM_REG_RISCV_ISA_MULTI_EN	(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)

#define KVM_REG_RISCV_ISA_MULTI_DIS	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)

#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id)	\

		((__ext_id) / __BITS_PER_LONG)

#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id)	\

		(1UL << ((__ext_id) % __BITS_PER_LONG))

#define KVM_REG_RISCV_ISA_MULTI_REG_LAST	\

		KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)



/* SBI extension registers are mapped as type 8 */

#define KVM_REG_RISCV_SBI_EXT		(0x08 << KVM_REG_RISCV_TYPE_SHIFT)