Commit e3cd0360 authored by chen gong's avatar chen gong Committed by Alex Deucher
Browse files

drm/amdgpu: read gfx register using RREG32_KIQ macro 



Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
hang when GPU is in "gfxoff" state.
I do a uniform substitution here.

Signed-off-by: default avatarchen gong <curry.gong@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c68dbcd8

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+5 −5
Original line number Diff line number Diff line
@@ -4717,12 +4717,12 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 
		*flags = 0;



	/* AMD_CG_SUPPORT_GFX_MGCG */

	data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));

	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))

		*flags |= AMD_CG_SUPPORT_GFX_MGCG;



	/* AMD_CG_SUPPORT_GFX_CGCG */

	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));

	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)

		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
@@ -4731,18 +4731,18 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 
		*flags |= AMD_CG_SUPPORT_GFX_CGLS;



	/* AMD_CG_SUPPORT_GFX_RLC_LS */

	data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));

	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;



	/* AMD_CG_SUPPORT_GFX_CP_LS */

	data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));

	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)

		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;



	if (adev->asic_type != CHIP_ARCTURUS) {

		/* AMD_CG_SUPPORT_GFX_3D_CGCG */

		data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

		data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));

		if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)

			*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;