Commit e3c92eb4 authored by Somalapuram Amaranath's avatar Somalapuram Amaranath Committed by Christian König
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drm/ttm: rework on ttm_resource to use size_t type



Change ttm_resource structure from num_pages to size_t size in bytes.
v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
v1 -> v2: change bo->resource->size to bo->base.size at some places
v1 -> v2: remove the local variable
v1 -> v2: cleanup cmp_size_smaller_first()
v2 -> v3: adding missing PFN_UP in ttm_bo_vm_fault_reserved

Signed-off-by: default avatarSomalapuram Amaranath <Amaranath.Somalapuram@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221027091237.983582-1-Amaranath.Somalapuram@amd.com


Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
parent e1e7bc48
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+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
		node->base.start = node->mm_nodes[0].start;
	} else {
		node->mm_nodes[0].start = 0;
		node->mm_nodes[0].size = node->base.num_pages;
		node->mm_nodes[0].size = PFN_UP(node->base.size);
		node->base.start = AMDGPU_BO_INVALID_OFFSET;
	}

+2 −1
Original line number Diff line number Diff line
@@ -542,6 +542,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
		/* GWS and OA don't need any alignment. */
		page_align = bp->byte_align;
		size <<= PAGE_SHIFT;

	} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
		/* Both size and alignment must be a multiple of 4. */
		page_align = ALIGN(bp->byte_align, 4);
@@ -776,7 +777,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
		return 0;
	}

	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
	r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
	if (r)
		return r;

+2 −2
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
	if (!res)
		goto fallback;

	BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
	BUG_ON(start + size > res->size);

	cur->mem_type = res->mem_type;

@@ -110,7 +110,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
	cur->size = size;
	cur->remaining = size;
	cur->node = NULL;
	WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
	WARN_ON(res && start + size > res->size);
	return;
}

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ TRACE_EVENT(amdgpu_bo_create,

	    TP_fast_assign(
			   __entry->bo = bo;
			   __entry->pages = bo->tbo.resource->num_pages;
			   __entry->pages = PFN_UP(bo->tbo.resource->size);
			   __entry->type = bo->tbo.resource->mem_type;
			   __entry->prefer = bo->preferred_domains;
			   __entry->allow = bo->allowed_domains;
+3 −3
Original line number Diff line number Diff line
@@ -381,7 +381,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
	dst.offset = 0;

	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
				       new_mem->num_pages << PAGE_SHIFT,
				       new_mem->size,
				       amdgpu_bo_encrypted(abo),
				       bo->base.resv, &fence);
	if (r)
@@ -424,7 +424,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
static bool amdgpu_mem_visible(struct amdgpu_device *adev,
			       struct ttm_resource *mem)
{
	u64 mem_size = (u64)mem->num_pages << PAGE_SHIFT;
	u64 mem_size = (u64)mem->size;
	struct amdgpu_res_cursor cursor;
	u64 end;

@@ -568,7 +568,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
				     struct ttm_resource *mem)
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
	size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
	size_t bus_size = (size_t)mem->size;

	switch (mem->mem_type) {
	case TTM_PL_SYSTEM:
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