Unverified Commit e3c68ab1 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-fixes-5.16-2' of... 

Merge tag 'imx-fixes-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.16, round 2:

- One fix on imx8m-blk-ctrl driver to get i.MX8MM MIPI reset work
  properly
- Fix CSI_DATA07__ESAI_TX0 pad name in i.MX7ULL pin function header
- Remove interconnect property from i.MX8MQ LCDIF device to fix the
  regression that LCDIF driver stops probe, because interconnect
  provider driver (imx-bus) hasn't been fully working.
- Fix soc-imx driver to register SoC device only on i.MX platform.

* tag 'imx-fixes-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: Register SoC device only on i.MX boards
  soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi reset
  ARM: dts: imx6ull-pinfunc: Fix CSI_DATA07__ESAI_TX0 pad name
  arm64: dts: imx8mq: remove interconnect property from lcdif

Link: https://lore.kernel.org/r/20211211015625.GK4216@dragon


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7ad1a90a 4ebd29f9

arch/arm/boot/dts/imx6ull-pinfunc.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -82,6 +82,6 @@ 
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA07__ESAI_T0                            0x0200 0x048C 0x0000 0x9 0x0

#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0                           0x0200 0x048C 0x0000 0x9 0x0





#endif /* __DTS_IMX6ULL_PINFUNC_H */
 
#endif /* __DTS_IMX6ULL_PINFUNC_H */

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+0 −2
Original line number Original line Diff line number Diff line
@@ -524,8 +524,6 @@ 
						  <&clk IMX8MQ_VIDEO_PLL1>,

						  <&clk IMX8MQ_VIDEO_PLL1>,

						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;

						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;

				assigned-clock-rates = <0>, <0>, <0>, <594000000>;

				assigned-clock-rates = <0>, <0>, <0>, <594000000>;

				interconnects = <&noc IMX8MQ_ICM_LCDIF &noc IMX8MQ_ICS_DRAM>;

				interconnect-names = "dram";

				status = "disabled";

				status = "disabled";





				port@0 {

				port@0 {

drivers/soc/imx/imx8m-blk-ctrl.c

+19 −0
Original line number Original line Diff line number Diff line
@@ -17,6 +17,7 @@ 




#define BLK_SFT_RSTN	0x0

#define BLK_SFT_RSTN	0x0

#define BLK_CLK_EN	0x4

#define BLK_CLK_EN	0x4

#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */





struct imx8m_blk_ctrl_domain;

struct imx8m_blk_ctrl_domain;
@@ -36,6 +37,15 @@ struct imx8m_blk_ctrl_domain_data { 
	const char *gpc_name;

	const char *gpc_name;

	u32 rst_mask;

	u32 rst_mask;

	u32 clk_mask;

	u32 clk_mask;



	/*

	 * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register

	 * which is used to control the reset for the MIPI Phy.

	 * Since it's only present in certain circumstances,

	 * an if-statement should be used before setting and clearing this

	 * register.

	 */

	u32 mipi_phy_rst_mask;

};

};





#define DOMAIN_MAX_CLKS 3

#define DOMAIN_MAX_CLKS 3
@@ -78,6 +88,8 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) 




	/* put devices into reset */

	/* put devices into reset */

	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	if (data->mipi_phy_rst_mask)

		regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);





	/* enable upstream and blk-ctrl clocks to allow reset to propagate */

	/* enable upstream and blk-ctrl clocks to allow reset to propagate */

	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);

	ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);
@@ -99,6 +111,8 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) 




	/* release reset */

	/* release reset */

	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	if (data->mipi_phy_rst_mask)

		regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);





	/* disable upstream clocks */

	/* disable upstream clocks */

	clk_bulk_disable_unprepare(data->num_clks, domain->clks);

	clk_bulk_disable_unprepare(data->num_clks, domain->clks);
@@ -120,6 +134,9 @@ static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) 
	struct imx8m_blk_ctrl *bc = domain->bc;

	struct imx8m_blk_ctrl *bc = domain->bc;





	/* put devices into reset and disable clocks */

	/* put devices into reset and disable clocks */

	if (data->mipi_phy_rst_mask)

		regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);



	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);

	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);

	regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
@@ -480,6 +497,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] 
		.gpc_name = "mipi-dsi",

		.gpc_name = "mipi-dsi",

		.rst_mask = BIT(5),

		.rst_mask = BIT(5),

		.clk_mask = BIT(8) | BIT(9),

		.clk_mask = BIT(8) | BIT(9),

		.mipi_phy_rst_mask = BIT(17),

	},

	},

	[IMX8MM_DISPBLK_PD_MIPI_CSI] = {

	[IMX8MM_DISPBLK_PD_MIPI_CSI] = {

		.name = "dispblk-mipi-csi",

		.name = "dispblk-mipi-csi",
@@ -488,6 +506,7 @@ static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] 
		.gpc_name = "mipi-csi",

		.gpc_name = "mipi-csi",

		.rst_mask = BIT(3) | BIT(4),

		.rst_mask = BIT(3) | BIT(4),

		.clk_mask = BIT(10) | BIT(11),

		.clk_mask = BIT(10) | BIT(11),

		.mipi_phy_rst_mask = BIT(16),

	},

	},

};

};

drivers/soc/imx/soc-imx.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,10 @@ static int __init imx_soc_device_init(void) 
	int ret;

	int ret;

	int i;

	int i;





	/* Return early if this is running on devices with different SoCs */

	if (!__mxc_cpu_type)

		return 0;



	if (of_machine_is_compatible("fsl,ls1021a"))

	if (of_machine_is_compatible("fsl,ls1021a"))

		return 0;

		return 0;