Unverified Commit e3c591c0 authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: SOF: Intel: update D0i3 registers for MTL 

Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

MeteorLake relies on a different register for D0i3 configuration, add
a platform-specific callback to abstract the differences.
parents 43b429f0 57f93492

sound/soc/sof/intel/apl.c

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ const struct sof_intel_dsp_desc apl_chip_info = { 
	.rom_init_timeout	= 150,

	.ssp_count = APL_SSP_COUNT,

	.ssp_base_offset = APL_SSP_BASE_OFFSET,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.quirks = SOF_INTEL_PROCEN_FMT_QUIRK,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/cnl.c

+2 −0
Original line number Diff line number Diff line
@@ -456,6 +456,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,
@@ -488,6 +489,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/hda-dsp.c

+14 −7
Original line number Diff line number Diff line
@@ -348,8 +348,12 @@ void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev) 
static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)

{

	int retry = HDA_DSP_REG_POLL_RETRY_COUNT;

	struct snd_sof_pdata *pdata = sdev->pdata;

	const struct sof_intel_dsp_desc *chip;



	while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C) & SOF_HDA_VS_D0I3C_CIP) {

	chip = get_chip_info(pdata);

	while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) &

		SOF_HDA_VS_D0I3C_CIP) {

		if (!retry--)

			return -ETIMEDOUT;

		usleep_range(10, 15);
@@ -377,29 +381,32 @@ static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags) 


static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)

{

	struct hdac_bus *bus = sof_to_bus(sdev);

	struct snd_sof_pdata *pdata = sdev->pdata;

	const struct sof_intel_dsp_desc *chip;

	int ret;

	u8 reg;



	chip = get_chip_info(pdata);



	/* Write to D0I3C after Command-In-Progress bit is cleared */

	ret = hda_dsp_wait_d0i3c_done(sdev);

	if (ret < 0) {

		dev_err(bus->dev, "CIP timeout before D0I3C update!\n");

		dev_err(sdev->dev, "CIP timeout before D0I3C update!\n");

		return ret;

	}



	/* Update D0I3C register */

	snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR,

			    SOF_HDA_VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);

	snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset,

			    SOF_HDA_VS_D0I3C_I3, value);



	/* Wait for cmd in progress to be cleared before exiting the function */

	ret = hda_dsp_wait_d0i3c_done(sdev);

	if (ret < 0) {

		dev_err(bus->dev, "CIP timeout after D0I3C update!\n");

		dev_err(sdev->dev, "CIP timeout after D0I3C update!\n");

		return ret;

	}



	reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, SOF_HDA_VS_D0I3C);

	reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset);

	trace_sof_intel_D0I3C_updated(sdev, reg);



	return 0;

sound/soc/sof/intel/icl.c

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ const struct sof_intel_dsp_desc icl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE,

	.sdw_alh_base = SDW_ALH_BASE,

	.d0i3_offset = SOF_HDA_VS_D0I3C,

	.check_sdw_irq	= hda_common_check_sdw_irq,

	.check_ipc_irq	= hda_dsp_check_ipc_irq,

	.cl_init = cl_dsp_init,

sound/soc/sof/intel/mtl.c

+1 −0
Original line number Diff line number Diff line
@@ -684,6 +684,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { 
	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

	.sdw_shim_base = SDW_SHIM_BASE_ACE,

	.sdw_alh_base = SDW_ALH_BASE_ACE,

	.d0i3_offset = MTL_HDA_VS_D0I3C,

	.check_sdw_irq = mtl_dsp_check_sdw_irq,

	.check_ipc_irq = mtl_dsp_check_ipc_irq,

	.cl_init = mtl_dsp_cl_init,