Commit e3b5ee0c authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge branches 'iommu/fixes', 'arm/smmu', 'x86/amd', 'x86/vt-d' and 'core' into next

parents 8c17bbf6 6855d1ba 154e3a65 857f0814 c11738cf

Documentation/devicetree/bindings/iommu/iommu.txt

+6 −0
Original line number Diff line number Diff line
@@ -86,6 +86,12 @@ have a means to turn off translation. But it is invalid in such cases to 
disable the IOMMU's device tree node in the first place because it would

prevent any driver from properly setting up the translations.



Optional properties:

--------------------

- pasid-num-bits: Some masters support multiple address spaces for DMA, by

  tagging DMA transactions with an address space identifier. By default,

  this is 0, which means that the device only has one address space.





Notes:

======

drivers/acpi/arm64/iort.c

+20 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#define pr_fmt(fmt)	"ACPI: IORT: " fmt



#include <linux/acpi_iort.h>

#include <linux/bitfield.h>

#include <linux/iommu.h>

#include <linux/kernel.h>

#include <linux/list.h>
@@ -850,9 +851,9 @@ static inline bool iort_iommu_driver_enabled(u8 type) 
{

	switch (type) {

	case ACPI_IORT_NODE_SMMU_V3:

		return IS_BUILTIN(CONFIG_ARM_SMMU_V3);

		return IS_ENABLED(CONFIG_ARM_SMMU_V3);

	case ACPI_IORT_NODE_SMMU:

		return IS_BUILTIN(CONFIG_ARM_SMMU);

		return IS_ENABLED(CONFIG_ARM_SMMU);

	default:

		pr_warn("IORT node type %u does not describe an SMMU\n", type);

		return false;
@@ -924,6 +925,20 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) 
	return iort_iommu_xlate(info->dev, parent, streamid);

}



static void iort_named_component_init(struct device *dev,

				      struct acpi_iort_node *node)

{

	struct acpi_iort_named_component *nc;

	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);



	if (!fwspec)

		return;



	nc = (struct acpi_iort_named_component *)node->node_data;

	fwspec->num_pasid_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS,

					   nc->node_flags);

}



/**

 * iort_iommu_configure - Set-up IOMMU configuration for a device.

 *
@@ -978,6 +993,9 @@ const struct iommu_ops *iort_iommu_configure(struct device *dev) 
			if (parent)

				err = iort_iommu_xlate(dev, parent, streamid);

		} while (parent && !err);



		if (!err)

			iort_named_component_init(dev, node);

	}



	/*

drivers/iommu/Kconfig

+30 −5
Original line number Diff line number Diff line
@@ -214,6 +214,7 @@ config INTEL_IOMMU_SVM 
	select PCI_PASID

	select PCI_PRI

	select MMU_NOTIFIER

	select IOASID

	help

	  Shared Virtual Memory (SVM) provides a facility for devices

	  to access DMA resources through process address space by
@@ -248,6 +249,18 @@ config INTEL_IOMMU_FLOPPY_WA 
	  workaround will setup a 1:1 mapping for the first

	  16MiB to make floppy (an ISA device) work.



config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON

	bool "Enable Intel IOMMU scalable mode by default"

	depends on INTEL_IOMMU

	help

	  Selecting this option will enable by default the scalable mode if

	  hardware presents the capability. The scalable mode is defined in

	  VT-d 3.0. The scalable mode capability could be checked by reading

	  /sys/devices/virtual/iommu/dmar*/intel-iommu/ecap. If this option

	  is not selected, scalable mode support could also be enabled by

	  passing intel_iommu=sm_on to the kernel. If not sure, please use

	  the default value.



config IRQ_REMAP

	bool "Support for Interrupt Remapping"

	depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI
@@ -356,7 +369,7 @@ config SPAPR_TCE_IOMMU 


# ARM IOMMU support

config ARM_SMMU

	bool "ARM Ltd. System MMU (SMMU) Support"

	tristate "ARM Ltd. System MMU (SMMU) Support"

	depends on (ARM64 || ARM) && MMU

	select IOMMU_API

	select IOMMU_IO_PGTABLE_LPAE
@@ -368,6 +381,18 @@ config ARM_SMMU 
	  Say Y here if your SoC includes an IOMMU device implementing

	  the ARM SMMU architecture.



config ARM_SMMU_LEGACY_DT_BINDINGS

	bool "Support the legacy \"mmu-masters\" devicetree bindings"

	depends on ARM_SMMU=y && OF

	help

	  Support for the badly designed and deprecated "mmu-masters"

	  devicetree bindings. This allows some DMA masters to attach

	  to the SMMU but does not provide any support via the DMA API.

	  If you're lucky, you might be able to get VFIO up and running.



	  If you say Y here then you'll make me very sad. Instead, say N

	  and move your firmware to the utopian future that was 2016.



config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT

	bool "Default to disabling bypass on ARM SMMU v1 and v2"

	depends on ARM_SMMU
@@ -394,7 +419,7 @@ config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT 
	  config.



config ARM_SMMU_V3

	bool "ARM Ltd. System MMU Version 3 (SMMUv3) Support"

	tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support"

	depends on ARM64

	select IOMMU_API

	select IOMMU_IO_PGTABLE_LPAE

drivers/iommu/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -14,7 +14,8 @@ obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o 
obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o amd_iommu_init.o amd_iommu_quirks.o

obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += amd_iommu_debugfs.o

obj-$(CONFIG_AMD_IOMMU_V2) += amd_iommu_v2.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu.o arm-smmu-impl.o arm-smmu-qcom.o

obj-$(CONFIG_ARM_SMMU) += arm-smmu-mod.o

arm-smmu-mod-objs += arm-smmu.o arm-smmu-impl.o arm-smmu-qcom.o

obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o

obj-$(CONFIG_DMAR_TABLE) += dmar.o

obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o intel-pasid.o

drivers/iommu/amd_iommu.c

+1 −11
Original line number Diff line number Diff line
@@ -2297,7 +2297,6 @@ int __init amd_iommu_init_api(void) 
int __init amd_iommu_init_dma_ops(void)

{

	swiotlb        = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;

	iommu_detected = 1;



	if (amd_iommu_unmap_flush)

		pr_info("IO/TLB flush on unmap enabled\n");
@@ -2641,15 +2640,6 @@ static void amd_iommu_get_resv_regions(struct device *dev, 
	list_add_tail(&region->list, head);

}



static void amd_iommu_put_resv_regions(struct device *dev,

				     struct list_head *head)

{

	struct iommu_resv_region *entry, *next;



	list_for_each_entry_safe(entry, next, head, list)

		kfree(entry);

}



static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,

					 struct device *dev)

{
@@ -2688,7 +2678,7 @@ const struct iommu_ops amd_iommu_ops = { 
	.device_group = amd_iommu_device_group,

	.domain_get_attr = amd_iommu_domain_get_attr,

	.get_resv_regions = amd_iommu_get_resv_regions,

	.put_resv_regions = amd_iommu_put_resv_regions,

	.put_resv_regions = generic_iommu_put_resv_regions,

	.is_attach_deferred = amd_iommu_is_attach_deferred,

	.pgsize_bitmap	= AMD_IOMMU_PGSIZES,

	.flush_iotlb_all = amd_iommu_flush_iotlb_all,