Commit e3849765 authored by Marc Zyngier's avatar Marc Zyngier Committed by Catalin Marinas
Browse files

arm64: Document the requirement for SCR_EL3.HCE 



It is amazing that we never documented this absolutely basic
requirement: if you boot the kernel at EL2, you'd better
enable the HVC instruction from EL3.

Really, just do it.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20210812190213.2601506-6-maz@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 90268574

Documentation/arm64/booting.rst

+11 −4
Original line number Diff line number Diff line
@@ -207,11 +207,18 @@ Before jumping into the kernel, the following conditions must be met: 
  software at a higher exception level to prevent execution in an UNKNOWN

  state.



  For all systems:

  - If EL3 is present:



    - SCR_EL3.FIQ must have the same value across all CPUs the kernel is

      executing on.

    - The value of SCR_EL3.FIQ must be the same as the one present at boot

      time whenever the kernel is executing.



  - If EL3 is present and the kernel is entered at EL2:



    - SCR_EL3.HCE (bit 8) must be initialised to 0b1.



  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present: