Commit e35d13a5 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Lorenzo Pieralisi
Browse files

PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 

The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the
v2.3.2 sequence which now also disables hotplug capability of the
controller as it is not at all supported on any SoCs making use of this IP.

Link: https://lore.kernel.org/r/20230619150408.8468-8-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 25966e78

drivers/pci/controller/dwc/pcie-qcom.c

+1 −29
Original line number Diff line number Diff line
@@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 
	return 0;

}



static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)

{

	u32 val;



	/* enable PCIe clocks and resets */

	val = readl(pcie->parf + PARF_PHY_CTRL);

	val &= ~PHY_TEST_PWR_DOWN;

	writel(val, pcie->parf + PARF_PHY_CTRL);



	/* change DBI base address */

	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);



	/* MAC PHY_POWERDOWN MUX DISABLE  */

	val = readl(pcie->parf + PARF_SYS_CTRL);

	val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;

	writel(val, pcie->parf + PARF_SYS_CTRL);



	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);

	val |= BYPASS;

	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);



	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);

	val |= EN;

	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);



	return 0;

}



static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)

{

	struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
@@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = { 
static const struct qcom_pcie_ops ops_2_4_0 = {

	.get_resources = qcom_pcie_get_resources_2_4_0,

	.init = qcom_pcie_init_2_4_0,

	.post_init = qcom_pcie_post_init_2_4_0,

	.post_init = qcom_pcie_post_init_2_3_2,

	.deinit = qcom_pcie_deinit_2_4_0,

	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

};