Commit e31a8cf5 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-cleanups' 



Guangbin Huang says:

====================
net: hns3: add some cleanups

This series includes some cleanups for the HNS3 ethernet driver.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents fe50893a 0c5c135c

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+2 −3
Original line number Diff line number Diff line
@@ -38,9 +38,8 @@ static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 
	},

};



static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd);

static int hns3_dbg_common_file_init(struct hnae3_handle *handle,

				     unsigned int cmd);

static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd);

static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd);



static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {

	{

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+19 −10
Original line number Diff line number Diff line
@@ -5063,6 +5063,24 @@ void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 
	hns3_set_cq_period_mode(priv, rx_mode, false);

}



static void hns3_state_init(struct hnae3_handle *handle)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);

	struct net_device *netdev = handle->kinfo.netdev;

	struct hns3_nic_priv *priv = netdev_priv(netdev);



	set_bit(HNS3_NIC_STATE_INITED, &priv->state);



	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)

		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);



	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))

		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);



	if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))

		set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);

}



static int hns3_client_init(struct hnae3_handle *handle)

{

	struct pci_dev *pdev = handle->pdev;
@@ -5166,16 +5184,7 @@ static int hns3_client_init(struct hnae3_handle *handle) 


	netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);



	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))

		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);



	if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))

		set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);



	set_bit(HNS3_NIC_STATE_INITED, &priv->state);



	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)

		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);

	hns3_state_init(handle);



	ret = register_netdev(netdev);

	if (ret) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+13 −10
Original line number Diff line number Diff line
@@ -1017,16 +1017,6 @@ struct hclge_common_lb_cmd { 


#define HCLGE_TYPE_CRQ			0

#define HCLGE_TYPE_CSQ			1

#define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000

#define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004

#define HCLGE_NIC_CSQ_DEPTH_REG		0x27008

#define HCLGE_NIC_CSQ_TAIL_REG		0x27010

#define HCLGE_NIC_CSQ_HEAD_REG		0x27014

#define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018

#define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701c

#define HCLGE_NIC_CRQ_DEPTH_REG		0x27020

#define HCLGE_NIC_CRQ_TAIL_REG		0x27024

#define HCLGE_NIC_CRQ_HEAD_REG		0x27028



/* this bit indicates that the driver is ready for hardware reset */

#define HCLGE_NIC_SW_RST_RDY_B		16
@@ -1201,6 +1191,19 @@ struct hclge_dev_specs_1_cmd { 
	u8 rsv1[18];

};



/* mac speed type defined in firmware command */

enum HCLGE_FIRMWARE_MAC_SPEED {

	HCLGE_FW_MAC_SPEED_1G,

	HCLGE_FW_MAC_SPEED_10G,

	HCLGE_FW_MAC_SPEED_25G,

	HCLGE_FW_MAC_SPEED_40G,

	HCLGE_FW_MAC_SPEED_50G,

	HCLGE_FW_MAC_SPEED_100G,

	HCLGE_FW_MAC_SPEED_10M,

	HCLGE_FW_MAC_SPEED_100M,

	HCLGE_FW_MAC_SPEED_200G,

};



#define HCLGE_PHY_LINK_SETTING_BD_NUM		2



struct hclge_phy_link_ksetting_0_cmd {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+29 −29
Original line number Diff line number Diff line
@@ -92,23 +92,23 @@ static const struct pci_device_id ae_algo_pci_tbl[] = { 


MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);



static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,

					 HCLGE_CMDQ_TX_ADDR_H_REG,

					 HCLGE_CMDQ_TX_DEPTH_REG,

					 HCLGE_CMDQ_TX_TAIL_REG,

					 HCLGE_CMDQ_TX_HEAD_REG,

					 HCLGE_CMDQ_RX_ADDR_L_REG,

					 HCLGE_CMDQ_RX_ADDR_H_REG,

					 HCLGE_CMDQ_RX_DEPTH_REG,

					 HCLGE_CMDQ_RX_TAIL_REG,

					 HCLGE_CMDQ_RX_HEAD_REG,

static const u32 cmdq_reg_addr_list[] = {HCLGE_NIC_CSQ_BASEADDR_L_REG,

					 HCLGE_NIC_CSQ_BASEADDR_H_REG,

					 HCLGE_NIC_CSQ_DEPTH_REG,

					 HCLGE_NIC_CSQ_TAIL_REG,

					 HCLGE_NIC_CSQ_HEAD_REG,

					 HCLGE_NIC_CRQ_BASEADDR_L_REG,

					 HCLGE_NIC_CRQ_BASEADDR_H_REG,

					 HCLGE_NIC_CRQ_DEPTH_REG,

					 HCLGE_NIC_CRQ_TAIL_REG,

					 HCLGE_NIC_CRQ_HEAD_REG,

					 HCLGE_VECTOR0_CMDQ_SRC_REG,

					 HCLGE_CMDQ_INTR_STS_REG,

					 HCLGE_CMDQ_INTR_EN_REG,

					 HCLGE_CMDQ_INTR_GEN_REG};



static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,

					   HCLGE_VECTOR0_OTER_EN_REG,

					   HCLGE_PF_OTHER_INT_REG,

					   HCLGE_MISC_RESET_STS_REG,

					   HCLGE_MISC_VECTOR_INT_STS,

					   HCLGE_GLOBAL_RESET_REG,
@@ -959,31 +959,31 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) 
static int hclge_parse_speed(u8 speed_cmd, u32 *speed)

{

	switch (speed_cmd) {

	case 6:

	case HCLGE_FW_MAC_SPEED_10M:

		*speed = HCLGE_MAC_SPEED_10M;

		break;

	case 7:

	case HCLGE_FW_MAC_SPEED_100M:

		*speed = HCLGE_MAC_SPEED_100M;

		break;

	case 0:

	case HCLGE_FW_MAC_SPEED_1G:

		*speed = HCLGE_MAC_SPEED_1G;

		break;

	case 1:

	case HCLGE_FW_MAC_SPEED_10G:

		*speed = HCLGE_MAC_SPEED_10G;

		break;

	case 2:

	case HCLGE_FW_MAC_SPEED_25G:

		*speed = HCLGE_MAC_SPEED_25G;

		break;

	case 3:

	case HCLGE_FW_MAC_SPEED_40G:

		*speed = HCLGE_MAC_SPEED_40G;

		break;

	case 4:

	case HCLGE_FW_MAC_SPEED_50G:

		*speed = HCLGE_MAC_SPEED_50G;

		break;

	case 5:

	case HCLGE_FW_MAC_SPEED_100G:

		*speed = HCLGE_MAC_SPEED_100G;

		break;

	case 8:

	case HCLGE_FW_MAC_SPEED_200G:

		*speed = HCLGE_MAC_SPEED_200G;

		break;

	default:
@@ -2582,39 +2582,39 @@ static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 
	switch (speed) {

	case HCLGE_MAC_SPEED_10M:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 6);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10M);

		break;

	case HCLGE_MAC_SPEED_100M:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 7);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100M);

		break;

	case HCLGE_MAC_SPEED_1G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 0);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_1G);

		break;

	case HCLGE_MAC_SPEED_10G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 1);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10G);

		break;

	case HCLGE_MAC_SPEED_25G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 2);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_25G);

		break;

	case HCLGE_MAC_SPEED_40G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 3);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_40G);

		break;

	case HCLGE_MAC_SPEED_50G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 4);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_50G);

		break;

	case HCLGE_MAC_SPEED_100G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 5);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100G);

		break;

	case HCLGE_MAC_SPEED_200G:

		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,

				HCLGE_CFG_SPEED_S, 8);

				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_200G);

		break;

	default:

		dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+11 −11
Original line number Diff line number Diff line
@@ -38,22 +38,22 @@ 
#define HCLGE_VECTOR_REG_OFFSET_H	0x1000

#define HCLGE_VECTOR_VF_OFFSET		0x100000



#define HCLGE_CMDQ_TX_ADDR_L_REG	0x27000

#define HCLGE_CMDQ_TX_ADDR_H_REG	0x27004

#define HCLGE_CMDQ_TX_DEPTH_REG		0x27008

#define HCLGE_CMDQ_TX_TAIL_REG		0x27010

#define HCLGE_CMDQ_TX_HEAD_REG		0x27014

#define HCLGE_CMDQ_RX_ADDR_L_REG	0x27018

#define HCLGE_CMDQ_RX_ADDR_H_REG	0x2701C

#define HCLGE_CMDQ_RX_DEPTH_REG		0x27020

#define HCLGE_CMDQ_RX_TAIL_REG		0x27024

#define HCLGE_CMDQ_RX_HEAD_REG		0x27028

#define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000

#define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004

#define HCLGE_NIC_CSQ_DEPTH_REG		0x27008

#define HCLGE_NIC_CSQ_TAIL_REG		0x27010

#define HCLGE_NIC_CSQ_HEAD_REG		0x27014

#define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018

#define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701C

#define HCLGE_NIC_CRQ_DEPTH_REG		0x27020

#define HCLGE_NIC_CRQ_TAIL_REG		0x27024

#define HCLGE_NIC_CRQ_HEAD_REG		0x27028



#define HCLGE_CMDQ_INTR_STS_REG		0x27104

#define HCLGE_CMDQ_INTR_EN_REG		0x27108

#define HCLGE_CMDQ_INTR_GEN_REG		0x2710C



/* bar registers for common func */

#define HCLGE_VECTOR0_OTER_EN_REG	0x20600

#define HCLGE_GRO_EN_REG		0x28000

#define HCLGE_RXD_ADV_LAYOUT_EN_REG	0x28008