Commit e300d955 authored by John W. Linville's avatar John W. Linville
Browse files

Merge branch 'master' of... 

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem

Conflicts:
	drivers/net/wireless/wl12xx/wl1271_cmd.h
parents 242647bc 815868e7

MAINTAINERS

+3 −6
Original line number Diff line number Diff line
@@ -313,11 +313,9 @@ S: Maintained 
F:	drivers/hwmon/adm1029.c



ADM8211 WIRELESS DRIVER

M:	Michael Wu <flamingice@sourmilk.net>

L:	linux-wireless@vger.kernel.org

W:	http://linuxwireless.org/

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mwu/mac80211-drivers.git

S:	Maintained

S:	Orphan

F:	drivers/net/wireless/adm8211.*



ADT746X FAN DRIVER
@@ -4251,10 +4249,9 @@ F: include/scsi/osd_* 
F:	fs/exofs/



P54 WIRELESS DRIVER

M:	Michael Wu <flamingice@sourmilk.net>

M:	Christian Lamparter <chunkeey@googlemail.com>

L:	linux-wireless@vger.kernel.org

W:	http://prism54.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/mwu/mac80211-drivers.git

W:	http://wireless.kernel.org/en/users/Drivers/p54

S:	Maintained

F:	drivers/net/wireless/p54/

drivers/net/wireless/adm8211.c

+4 −1
Original line number Diff line number Diff line
@@ -1903,7 +1903,7 @@ static int __devinit adm8211_probe(struct pci_dev *pdev, 
	if (err) {

		printk(KERN_ERR "%s (adm8211): Cannot register device\n",

		       pci_name(pdev));

		goto err_free_desc;

		goto err_free_eeprom;

	}



	printk(KERN_INFO "%s: hwaddr %pM, Rev 0x%02x\n",
@@ -1912,6 +1912,9 @@ static int __devinit adm8211_probe(struct pci_dev *pdev, 


	return 0;



 err_free_eeprom:

	kfree(priv->eeprom);



 err_free_desc:

	pci_free_consistent(pdev,

			    sizeof(struct adm8211_desc) * priv->rx_ring_size +

drivers/net/wireless/ath/ath9k/ar5008_initvals.h

+625 −694
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2008-2009 Atheros Communications Inc.

 * Copyright (c) 2010 Atheros Communications Inc.

 *

 * Permission to use, copy, modify, and/or distribute this software for any

 * purpose with or without fee is hereby granted, provided that the above
@@ -14,9 +14,6 @@ 
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 */



#ifndef INITVALS_AR5008_H

#define INITVALS_AR5008_H



static const u32 ar5416Modes[][6] = {

	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},

	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
@@ -84,6 +81,7 @@ static const u32 ar5416Modes[][6] = { 
};



static const u32 ar5416Common[][2] = {

	/* Addr      allmodes  */

	{0x0000000c, 0x00000000},

	{0x00000030, 0x00020015},

	{0x00000034, 0x00000005},
@@ -461,11 +459,13 @@ static const u32 ar5416Common[][2] = { 
};



static const u32 ar5416Bank0[][2] = {

	/* Addr      allmodes  */

	{0x000098b0, 0x1e5795e5},

	{0x000098e0, 0x02008020},

};



static const u32 ar5416BB_RfGain[][3] = {

	/* Addr      5G_HT20     5G_HT40   */

	{0x00009a00, 0x00000000, 0x00000000},

	{0x00009a04, 0x00000040, 0x00000040},

	{0x00009a08, 0x00000080, 0x00000080},
@@ -533,21 +533,24 @@ static const u32 ar5416BB_RfGain[][3] = { 
};



static const u32 ar5416Bank1[][2] = {

	/* Addr      allmodes  */

	{0x000098b0, 0x02108421},

	{0x000098ec, 0x00000008},

};



static const u32 ar5416Bank2[][2] = {

	/* Addr      allmodes  */

	{0x000098b0, 0x0e73ff17},

	{0x000098e0, 0x00000420},

};



static const u32 ar5416Bank3[][3] = {

	/* Addr      5G_HT20     5G_HT40   */

	{0x000098f0, 0x01400018, 0x01c00018},

};



static const u32 ar5416Bank6[][3] = {



	/* Addr      5G_HT20     5G_HT40   */

	{0x0000989c, 0x00000000, 0x00000000},

	{0x0000989c, 0x00000000, 0x00000000},

	{0x0000989c, 0x00000000, 0x00000000},
@@ -584,6 +587,7 @@ static const u32 ar5416Bank6[][3] = { 
};



static const u32 ar5416Bank6TPC[][3] = {

	/* Addr      5G_HT20     5G_HT40   */

	{0x0000989c, 0x00000000, 0x00000000},

	{0x0000989c, 0x00000000, 0x00000000},

	{0x0000989c, 0x00000000, 0x00000000},
@@ -620,12 +624,14 @@ static const u32 ar5416Bank6TPC[][3] = { 
};



static const u32 ar5416Bank7[][2] = {

	/* Addr      allmodes  */

	{0x0000989c, 0x00000500},

	{0x0000989c, 0x00000800},

	{0x000098cc, 0x0000000e},

};



static const u32 ar5416Addac[][2] = {

	/* Addr      allmodes  */

	{0x0000989c, 0x00000000},

	{0x0000989c, 0x00000003},

	{0x0000989c, 0x00000000},
@@ -665,78 +671,3 @@ static const u32 ar5416Addac[][2] = { 
	{0x000098cc, 0x00000000},

};

static const u32 ar5416Modes_9100[][6] = {

    { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },

    { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },

    { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },

    { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },

    { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },

    { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },

    { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },

    { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },

    { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },

    { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },

    { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },

    { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },

    { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },

    { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },

    { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },

    { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },

    { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },

    { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },

    { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },

    { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },

    { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },

    { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },

    { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },

    { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },

    { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },

    { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },

    { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },

    { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },

    { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },

    { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },

#ifdef TB243

    { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },

    { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },

    { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },

    { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },

#else

    { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },

    { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },

    { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },

    { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },

#endif

    { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },

    { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },

    { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },

    { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },

    { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },

    { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },

    { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },

    { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },

    { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },

    { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },

    { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },

    { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },

    { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },

    { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },

    { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },

    { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },

    { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },

    { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },

    { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },

    { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },

    { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },

    { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },

    { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },

    { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },

    { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },

    { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },

    { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },

    { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },

    { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },

    { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },

};



#endif /* INITVALS_AR5008_H */

drivers/net/wireless/ath/ath9k/ar5008_phy.c

+26 −103
Original line number Diff line number Diff line
@@ -1495,121 +1495,25 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 
static void ar5008_hw_do_getnf(struct ath_hw *ah,

			      int16_t nfarray[NUM_NF_READINGS])

{

	struct ath_common *common = ath9k_hw_common(ah);

	int16_t nf;



	nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ctl] [chain 0] is %d\n", nf);

	nfarray[0] = nf;

	nfarray[0] = sign_extend(nf, 9);



	nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ctl] [chain 1] is %d\n", nf);

	nfarray[1] = nf;

	nfarray[1] = sign_extend(nf, 9);



	nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ctl] [chain 2] is %d\n", nf);

	nfarray[2] = nf;

	nfarray[2] = sign_extend(nf, 9);



	nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ext] [chain 0] is %d\n", nf);

	nfarray[3] = nf;

	nfarray[3] = sign_extend(nf, 9);



	nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ext] [chain 1] is %d\n", nf);

	nfarray[4] = nf;

	nfarray[4] = sign_extend(nf, 9);



	nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);

	if (nf & 0x100)

		nf = 0 - ((nf ^ 0x1ff) + 1);

	ath_print(common, ATH_DBG_CALIBRATE,

		  "NF calibrated [ext] [chain 2] is %d\n", nf);

	nfarray[5] = nf;

}



static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)

{

	struct ath9k_nfcal_hist *h;

	int i, j;

	int32_t val;

	const u32 ar5416_cca_regs[6] = {

		AR_PHY_CCA,

		AR_PHY_CH1_CCA,

		AR_PHY_CH2_CCA,

		AR_PHY_EXT_CCA,

		AR_PHY_CH1_EXT_CCA,

		AR_PHY_CH2_EXT_CCA

	};

	u8 chainmask, rx_chain_status;



	rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);

	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))

		chainmask = 0x9;

	else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {

		if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))

			chainmask = 0x1B;

		else

			chainmask = 0x09;

	} else {

		if (rx_chain_status & 0x4)

			chainmask = 0x3F;

		else if (rx_chain_status & 0x2)

			chainmask = 0x1B;

		else

			chainmask = 0x09;

	}



	h = ah->nfCalHist;



	for (i = 0; i < NUM_NF_READINGS; i++) {

		if (chainmask & (1 << i)) {

			val = REG_READ(ah, ar5416_cca_regs[i]);

			val &= 0xFFFFFE00;

			val |= (((u32) (h[i].privNF) << 1) & 0x1ff);

			REG_WRITE(ah, ar5416_cca_regs[i], val);

		}

	}



	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

		    AR_PHY_AGC_CONTROL_ENABLE_NF);

	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);



	for (j = 0; j < 5; j++) {

		if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &

		     AR_PHY_AGC_CONTROL_NF) == 0)

			break;

		udelay(50);

	}



	ENABLE_REGWRITE_BUFFER(ah);



	for (i = 0; i < NUM_NF_READINGS; i++) {

		if (chainmask & (1 << i)) {

			val = REG_READ(ah, ar5416_cca_regs[i]);

			val &= 0xFFFFFE00;

			val |= (((u32) (-50) << 1) & 0x1ff);

			REG_WRITE(ah, ar5416_cca_regs[i], val);

		}

	}



	REGWRITE_BUFFER_FLUSH(ah);

	DISABLE_REGWRITE_BUFFER(ah);

	nfarray[5] = sign_extend(nf, 9);

}



/*
@@ -1676,10 +1580,27 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 
	aniState->cycleCount = 0;

}



static void ar5008_hw_set_nf_limits(struct ath_hw *ah)

{

	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;

	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;

	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;

	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;

	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;

	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;

}



void ar5008_hw_attach_phy_ops(struct ath_hw *ah)

{

	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	const u32 ar5416_cca_regs[6] = {

		AR_PHY_CCA,

		AR_PHY_CH1_CCA,

		AR_PHY_CH2_CCA,

		AR_PHY_EXT_CCA,

		AR_PHY_CH1_EXT_CCA,

		AR_PHY_CH2_EXT_CCA

	};



	priv_ops->rf_set_freq = ar5008_hw_set_channel;

	priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
@@ -1699,7 +1620,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah) 
	priv_ops->restore_chainmask = ar5008_restore_chainmask;

	priv_ops->set_diversity = ar5008_set_diversity;

	priv_ops->do_getnf = ar5008_hw_do_getnf;

	priv_ops->loadnf = ar5008_hw_loadnf;



	if (modparam_force_new_ani) {

		priv_ops->ani_control = ar5008_hw_ani_control_new;
@@ -1713,4 +1633,7 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah) 
		priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;

	else

		priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;



	ar5008_hw_set_nf_limits(ah);

	memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));

}

drivers/net/wireless/ath/ath9k/ar9001_initvals.h

+1291 −1188

File changed.

Preview size limit exceeded, changes collapsed.