Commit e2f233ec authored by Rob Herring's avatar Rob Herring
Browse files

spi: dt-bindings: sifive: Add missing 2nd register region 



The 'reg' description and example have a 2nd register region for memory
mapped flash, but the schema says there is only 1 region. Fix this.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: linux-spi@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Acked-by: default avatarMark Brown <broonie@kernel.org>
Acked-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 65994c09

Documentation/devicetree/bindings/spi/spi-sifive.yaml

+4 −5
Original line number Diff line number Diff line
@@ -32,11 +32,10 @@ properties: 
      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi



  reg:

    maxItems: 1



    description:

      Physical base address and size of SPI registers map

      A second (optional) range can indicate memory mapped flash

    minItems: 1

    items:

      - description: SPI registers region

      - description: Memory mapped flash region



  interrupts:

    maxItems: 1