Commit e2eef312 authored by Serge Semin's avatar Serge Semin Committed by Stephen Boyd
Browse files

clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent 



Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are
disabled.

Note the ID is intentionally set to -2 since we are going to add a one
more internal clock identifier in the next commit.

Fixes: 353afa3a ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20220929225402.9696-4-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 3c742088

drivers/clk/baikal-t1/ccu-div.c

+1 −0
Original line number Diff line number Diff line
@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init) 
		goto err_free_div;

	}

	parent_data.fw_name = div_init->parent_name;

	parent_data.name = div_init->parent_name;

	hw_init.parent_data = &parent_data;

	hw_init.num_parents = 1;

drivers/clk/baikal-t1/ccu-div.h

+6 −0
Original line number Diff line number Diff line
@@ -13,6 +13,12 @@ 
#include <linux/bits.h>

#include <linux/of.h>



/*

 * CCU Divider private clock IDs

 * @CCU_SYS_XGMAC_CLK: CCU XGMAC internal clock

 */

#define CCU_SYS_XGMAC_CLK		-2



/*

 * CCU Divider private flags

 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.

drivers/clk/baikal-t1/clk-ccu-div.c

+5 −3
Original line number Diff line number Diff line
@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = { 
			  "eth_clk", CCU_SYS_GMAC1_BASE, 5),

	CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",

			   "eth_clk", 10),

	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",

			  "eth_clk", CCU_SYS_XGMAC_BASE, 8),

	CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_CLK, "sys_xgmac_clk",

			  "eth_clk", CCU_SYS_XGMAC_BASE, 1),

	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",

			   "sys_xgmac_clk", 8),

	CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",

			   "eth_clk", 8),

			   "sys_xgmac_clk", 8),

	CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",

			  "eth_clk", CCU_SYS_USB_BASE, 10),

	CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",