Commit e2df4641 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Simplify init_el2_state to be non-VHE only 



As init_el2_state is now nVHE only, let's simplify it and drop
the VHE setup.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarDavid Brazdil <dbrazdil@google.com>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-9-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 19e87e13

arch/arm64/include/asm/el2_setup.h

+8 −25
Original line number Diff line number Diff line
@@ -32,16 +32,14 @@ 
 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in

 * EL2.

 */

.macro __init_el2_timers mode

.ifeqs "\mode", "nvhe"

.macro __init_el2_timers

	mrs	x0, cnthctl_el2

	orr	x0, x0, #3			// Enable EL1 physical timers

	msr	cnthctl_el2, x0

.endif

	msr	cntvoff_el2, xzr		// Clear virtual offset

.endm



.macro __init_el2_debug mode

.macro __init_el2_debug

	mrs	x1, id_aa64dfr0_el1

	sbfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4

	cmp	x0, #1
@@ -55,7 +53,6 @@ 
	ubfx	x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4

	cbz	x0, .Lskip_spe_\@		// Skip if SPE not present



.ifeqs "\mode", "nvhe"

	mrs_s	x0, SYS_PMBIDR_EL1              // If SPE available at EL2,

	and	x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)

	cbnz	x0, .Lskip_spe_el2_\@		// then permit sampling of physical
@@ -66,7 +63,6 @@ 
	mov	x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)

	orr	x2, x2, x0			// If we don't have VHE, then

						// use EL1&0 translation.

.endif



.Lskip_spe_\@:

	msr	mdcr_el2, x2			// Configure debug traps
@@ -142,37 +138,24 @@ 


/**

 * Initialize EL2 registers to sane values. This should be called early on all

 * cores that were booted in EL2.

 * cores that were booted in EL2. Note that everything gets initialised as

 * if VHE was not evailable. The kernel context will be upgraded to VHE

 * if possible later on in the boot process

 *

 * Regs: x0, x1 and x2 are clobbered.

 */

.macro init_el2_state mode

.ifnes "\mode", "vhe"

.ifnes "\mode", "nvhe"

.error "Invalid 'mode' argument"

.endif

.endif



.macro init_el2_state

	__init_el2_sctlr

	__init_el2_timers \mode

	__init_el2_debug \mode

	__init_el2_timers

	__init_el2_debug

	__init_el2_lor

	__init_el2_stage2

	__init_el2_gicv3

	__init_el2_hstr



	/*

	 * When VHE is not in use, early init of EL2 needs to be done here.

	 * When VHE _is_ in use, EL1 will not be used in the host and

	 * requires no configuration, and all non-hyp-specific EL2 setup

	 * will be done via the _EL1 system register aliases in __cpu_setup.

	 */

.ifeqs "\mode", "nvhe"

	__init_el2_nvhe_idregs

	__init_el2_nvhe_cptr

	__init_el2_nvhe_sve

	__init_el2_nvhe_prepare_eret

.endif

.endm



#endif /* __ARM_KVM_INIT_H__ */

arch/arm64/kernel/head.S

+1 −1
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 
	msr	hcr_el2, x0

	isb



	init_el2_state nvhe

	init_el2_state



	/* Hypervisor stub */

	adr_l	x0, __hyp_stub_vectors

arch/arm64/kvm/hyp/nvhe/hyp-init.S

+1 −1
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ SYM_CODE_START_LOCAL(__kvm_hyp_init_cpu) 
2:	msr	SPsel, #1			// We want to use SP_EL{1,2}



	/* Initialize EL2 CPU state to sane values. */

	init_el2_state nvhe			// Clobbers x0..x2

	init_el2_state				// Clobbers x0..x2



	/* Enable MMU, set vectors and stack. */

	mov	x0, x28