Commit e2b75ea5 authored by Chang S. Bae's avatar Chang S. Bae Committed by Jia, Yingbao
Browse files

intel_idle: Add a new flag to initialize the AMX state 

mainline inclusion
from mainline-v6.0
commit 9f011293
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/IB1H2A
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9f01129382774d98ec21526f13da26a0630ee3d8



-------------------------------------------------

Intel-SIG: commit 9f011293 intel_idle: Add a new flag to initialize the
AMX state
Backport for GNR intel_idle support and fix on 5.10

The non-initialized AMX state can be the cause of C-state demotion from C6
to C1E. This low-power idle state may improve power savings and thus result
in a higher available turbo frequency budget.

This behavior is implementation-specific. Initialize the state for the C6
entrance of Sapphire Rapids as needed.

Suggested-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarChang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: default avatarZhang Rui <rui.zhang@intel.com>
Link: https://lkml.kernel.org/r/20220614164116.5196-1-chang.seok.bae@intel.com


[ yingbao jia: amend commit log ]
Signed-off-by: default avataryingbao jia <yingbao.jia@intel.com>
parent e91bb028

drivers/idle/intel_idle.c

+23 −2
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ 
#include <asm/nospec-branch.h>

#include <asm/mwait.h>

#include <asm/msr.h>

#include <asm/fpu/api.h>



#define INTEL_IDLE_VERSION "0.5.1"
@@ -113,6 +114,11 @@ static unsigned int mwait_substates __initdata; 
 */

#define CPUIDLE_FLAG_IBRS		BIT(16)



/*

 * Initialize large xstate for the C6-state entrance.

 */

#define CPUIDLE_FLAG_INIT_XSTATE	BIT(17)



/*

 * MWAIT takes an 8-bit "hint" in EAX "suggesting"

 * the C-state (top nibble) and sub-state (bottom nibble)
@@ -183,6 +189,13 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev, 
	return ret;

}



static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,

				       struct cpuidle_driver *drv, int index)

{

	fpu_idle_fpregs();

	return __intel_idle(dev, drv, index);

}



/**

 * intel_idle_s2idle - Ask the processor to enter the given idle state.

 * @dev: cpuidle device of the target CPU.
@@ -198,8 +211,12 @@ static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev, 
static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,

				       struct cpuidle_driver *drv, int index)

{

	unsigned long eax = flg2MWAIT(drv->states[index].flags);

	unsigned long ecx = 1; /* break on interrupt flag */

	struct cpuidle_state *state = &drv->states[index];

	unsigned long eax = flg2MWAIT(state->flags);



	if (state->flags & CPUIDLE_FLAG_INIT_XSTATE)

		fpu_idle_fpregs();



	mwait_idle_with_hints(eax, ecx);
@@ -823,7 +840,8 @@ static struct cpuidle_state spr_cstates[] __initdata = { 
	{

		.name = "C6",

		.desc = "MWAIT 0x20",

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED |

					   CPUIDLE_FLAG_INIT_XSTATE,

		.exit_latency = 290,

		.target_residency = 800,

		.enter = &intel_idle,
@@ -1739,6 +1757,9 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv) 
			drv->states[drv->state_count].enter = intel_idle_ibrs;

		}



		if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_INIT_XSTATE)

			drv->states[drv->state_count].enter = intel_idle_xstate;



		if ((disabled_states_mask & BIT(drv->state_count)) ||

		    ((icpu->use_acpi || force_use_acpi) &&

		     intel_idle_off_by_default(mwait_hint) &&