Commit e2b34fa0 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nve0/fifo: add support for the flip completion swmthd 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 0d7614f0

drivers/gpu/drm/nouveau/nve0_fifo.c

+33 −4
Original line number Diff line number Diff line
@@ -294,6 +294,25 @@ nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit) 
	printk(" on channel 0x%010llx\n", (u64)inst << 12);

}



static int

nve0_fifo_page_flip(struct drm_device *dev, u32 chid)

{

	struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_channel *chan = NULL;

	unsigned long flags;

	int ret = -EINVAL;



	spin_lock_irqsave(&dev_priv->channels.lock, flags);

	if (likely(chid >= 0 && chid < priv->base.channels)) {

		chan = dev_priv->channels.ptr[chid];

		if (likely(chan))

			ret = nouveau_finish_page_flip(chan, NULL);

	}

	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);

	return ret;

}



static void

nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)

{
@@ -303,11 +322,21 @@ nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit) 
	u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;

	u32 subc = (addr & 0x00070000);

	u32 mthd = (addr & 0x00003ffc);

	u32 show = stat;



	if (stat & 0x00200000) {

		if (mthd == 0x0054) {

			if (!nve0_fifo_page_flip(dev, chid))

				show &= ~0x00200000;

		}

	}



	NV_INFO(dev, "PSUBFIFO %d:", unit);

	nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);

	NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",

	if (show) {

		NV_INFO(dev, "PFIFO%d:", unit);

		nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);

		NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",

			unit, chid, subc, mthd, data);

	}



	nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);

	nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);