Commit e2980ba5 authored by Damian Muszynski's avatar Damian Muszynski Committed by Herbert Xu
Browse files

crypto: qat - add measure clock frequency 



The QAT hardware does not expose a mechanism to report its clock
frequency. This is required to implement the Heartbeat feature.

Add a clock measuring algorithm that estimates the frequency by
comparing the internal timestamp counter incremented by the firmware
with the time measured by the kernel.
The frequency value is only used internally and not exposed to
the user.

Signed-off-by: default avatarDamian Muszynski <damian.muszynski@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 7f77b679

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

+10 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <linux/iopoll.h>

#include <adf_accel_devices.h>

#include <adf_cfg.h>

#include <adf_clock.h>

#include <adf_common_drv.h>

#include <adf_gen4_dc.h>

#include <adf_gen4_hw_data.h>
@@ -318,6 +319,14 @@ static void get_admin_info(struct admin_info *admin_csrs_info) 
	admin_csrs_info->admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;

}



static u32 get_heartbeat_clock(struct adf_hw_device_data *self)

{

	/*

	 * 4XXX uses KPT counter for HB

	 */

	return ADF_4XXX_KPT_COUNTER_FREQ;

}



static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)

{

	struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];
@@ -511,6 +520,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id) 
	hw_data->dev_config = adf_gen4_dev_config;

	hw_data->start_timer = adf_gen4_timer_start;

	hw_data->stop_timer = adf_gen4_timer_stop;

	hw_data->get_hb_clock = get_heartbeat_clock;



	adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);

	adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.h

+4 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#ifndef ADF_4XXX_HW_DATA_H_

#define ADF_4XXX_HW_DATA_H_



#include <linux/units.h>

#include <adf_accel_devices.h>



/* PCIe configuration space */
@@ -64,6 +65,9 @@ 
#define ADF_402XX_ASYM_OBJ	"qat_402xx_asym.bin"

#define ADF_402XX_ADMIN_OBJ	"qat_402xx_admin.bin"



/* Clocks frequency */

#define ADF_4XXX_KPT_COUNTER_FREQ (100 * HZ_PER_MHZ)



/* qat_4xxx fuse bits are different from old GENs, redefine them */

enum icp_qat_4xxx_slice_mask {

	ICP_ACCEL_4XXX_MASK_CIPHER_SLICE = BIT(0),

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c

+25 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)

/* Copyright(c) 2014 - 2021 Intel Corporation */

#include <adf_accel_devices.h>

#include <adf_clock.h>

#include <adf_common_drv.h>

#include <adf_gen2_config.h>

#include <adf_gen2_dc.h>
@@ -50,6 +51,28 @@ static u32 get_ae_mask(struct adf_hw_device_data *self) 
	return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;

}



static u32 get_ts_clock(struct adf_hw_device_data *self)

{

	/*

	 * Timestamp update interval is 16 AE clock ticks for c3xxx.

	 */

	return self->clock_frequency / 16;

}



static int measure_clock(struct adf_accel_dev *accel_dev)

{

	u32 frequency;

	int ret;



	ret = adf_dev_measure_clock(accel_dev, &frequency, ADF_C3XXX_MIN_AE_FREQ,

				    ADF_C3XXX_MAX_AE_FREQ);

	if (ret)

		return ret;



	accel_dev->hw_device->clock_frequency = frequency;

	return 0;

}



static u32 get_misc_bar_id(struct adf_hw_device_data *self)

{

	return ADF_C3XXX_PMISC_BAR;
@@ -127,6 +150,8 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) 
	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

	hw_data->disable_iov = adf_disable_sriov;

	hw_data->dev_config = adf_gen2_dev_config;

	hw_data->measure_clock = measure_clock;

	hw_data->get_hb_clock = get_ts_clock;



	adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);

drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.h

+7 −0
Original line number Diff line number Diff line
@@ -3,6 +3,8 @@ 
#ifndef ADF_C3XXX_HW_DATA_H_

#define ADF_C3XXX_HW_DATA_H_



#include <linux/units.h>



/* PCIe configuration space */

#define ADF_C3XXX_PMISC_BAR 0

#define ADF_C3XXX_ETR_BAR 1
@@ -19,6 +21,11 @@ 
#define ADF_C3XXX_AE2FUNC_MAP_GRP_A_NUM_REGS 48

#define ADF_C3XXX_AE2FUNC_MAP_GRP_B_NUM_REGS 6



/* Clocks frequency */

#define ADF_C3XXX_AE_FREQ (685 * HZ_PER_MHZ)

#define ADF_C3XXX_MIN_AE_FREQ (533 * HZ_PER_MHZ)

#define ADF_C3XXX_MAX_AE_FREQ (685 * HZ_PER_MHZ)



/* Firmware Binary */

#define ADF_C3XXX_FW "qat_c3xxx.bin"

#define ADF_C3XXX_MMP "qat_c3xxx_mmp.bin"

drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

+25 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)

/* Copyright(c) 2014 - 2021 Intel Corporation */

#include <adf_accel_devices.h>

#include <adf_clock.h>

#include <adf_common_drv.h>

#include <adf_gen2_config.h>

#include <adf_gen2_dc.h>
@@ -50,6 +51,28 @@ static u32 get_ae_mask(struct adf_hw_device_data *self) 
	return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;

}



static u32 get_ts_clock(struct adf_hw_device_data *self)

{

	/*

	 * Timestamp update interval is 16 AE clock ticks for c62x.

	 */

	return self->clock_frequency / 16;

}



static int measure_clock(struct adf_accel_dev *accel_dev)

{

	u32 frequency;

	int ret;



	ret = adf_dev_measure_clock(accel_dev, &frequency, ADF_C62X_MIN_AE_FREQ,

				    ADF_C62X_MAX_AE_FREQ);

	if (ret)

		return ret;



	accel_dev->hw_device->clock_frequency = frequency;

	return 0;

}



static u32 get_misc_bar_id(struct adf_hw_device_data *self)

{

	return ADF_C62X_PMISC_BAR;
@@ -129,6 +152,8 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data) 
	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;

	hw_data->disable_iov = adf_disable_sriov;

	hw_data->dev_config = adf_gen2_dev_config;

	hw_data->measure_clock = measure_clock;

	hw_data->get_hb_clock = get_ts_clock;



	adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);

	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);