Commit e27525cc authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Namespace pfit registers properly 



Give the PFIT_CONTROL bits a consistent namespace.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 08df6d30

drivers/gpu/drm/i915/display/intel_lvds.c

+1 −1
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, 
	if (DISPLAY_VER(dev_priv) < 4) {

		tmp = intel_de_read(dev_priv, PFIT_CONTROL);



		crtc_state->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;

		crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;

	}



	crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;

drivers/gpu/drm/i915/display/intel_overlay.c

+1 −1
Original line number Diff line number Diff line
@@ -948,7 +948,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 
	} else {

		u32 tmp;



		if (intel_de_read(dev_priv, PFIT_CONTROL) & VERT_AUTO_SCALE)

		if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)

			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);

		else

			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);

drivers/gpu/drm/i915/display/intel_panel.c

+13 −12
Original line number Diff line number Diff line
@@ -567,8 +567,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state, 
			*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |

					     PFIT_VERT_SCALE(bits));

			*pfit_control |= (PFIT_ENABLE |

					  VERT_INTERP_BILINEAR |

					  HORIZ_INTERP_BILINEAR);

					  PFIT_VERT_INTERP_BILINEAR |

					  PFIT_HORIZ_INTERP_BILINEAR);

		}

	} else if (scaled_width < scaled_height) { /* letter */

		centre_vertically(adjusted_mode,
@@ -582,15 +582,16 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state, 
			*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |

					     PFIT_VERT_SCALE(bits));

			*pfit_control |= (PFIT_ENABLE |

					  VERT_INTERP_BILINEAR |

					  HORIZ_INTERP_BILINEAR);

					  PFIT_VERT_INTERP_BILINEAR |

					  PFIT_HORIZ_INTERP_BILINEAR);

		}

	} else {

		/* Aspects match, Let hw scale both directions */

		*pfit_control |= (PFIT_ENABLE |

				  VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |

				  VERT_INTERP_BILINEAR |

				  HORIZ_INTERP_BILINEAR);

				  PFIT_VERT_AUTO_SCALE |

				  PFIT_HORIZ_AUTO_SCALE |

				  PFIT_VERT_INTERP_BILINEAR |

				  PFIT_HORIZ_INTERP_BILINEAR);

	}

}
@@ -638,10 +639,10 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state, 
			if (DISPLAY_VER(dev_priv) >= 4)

				pfit_control |= PFIT_SCALING_AUTO;

			else

				pfit_control |= (VERT_AUTO_SCALE |

						 VERT_INTERP_BILINEAR |

						 HORIZ_AUTO_SCALE |

						 HORIZ_INTERP_BILINEAR);

				pfit_control |= (PFIT_VERT_AUTO_SCALE |

						 PFIT_VERT_INTERP_BILINEAR |

						 PFIT_HORIZ_AUTO_SCALE |

						 PFIT_HORIZ_INTERP_BILINEAR);

		}

		break;

	default:
@@ -662,7 +663,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state, 


	/* Make sure pre-965 set dither correctly for 18bpp panels. */

	if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)

		pfit_control |= PANEL_8TO6_DITHER_ENABLE;

		pfit_control |= PFIT_PANEL_8TO6_DITHER_ENABLE;



	crtc_state->gmch_pfit.control = pfit_control;

	crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;

drivers/gpu/drm/i915/i915_reg.h

+7 −7
Original line number Diff line number Diff line
@@ -2339,13 +2339,13 @@ 
#define   PFIT_FILTER_FUZZY		REG_FIELD_PREP(PFIT_FILTER_MASK, 0)

#define   PFIT_FILTER_CRISP		REG_FIELD_PREP(PFIT_FILTER_MASK, 1)

#define   PFIT_FILTER_MEDIAN		REG_FIELD_PREP(PFIT_FILTER_MASK, 2)

#define   VERT_INTERP_MASK		REG_GENMASK(11, 10) /* pre-965 */

#define   VERT_INTERP_BILINEAR		REG_FIELD_PREP(VERT_INTERP_MASK, 1)

#define   VERT_AUTO_SCALE		REG_BIT(9) /* pre-965 */

#define   HORIZ_INTERP_MASK		REG_GENMASK(7, 6) /* pre-965 */

#define   HORIZ_INTERP_BILINEAR		REG_FIELD_PREP(HORIZ_INTERP_MASK, 1)

#define   HORIZ_AUTO_SCALE		REG_BIT(5) /* pre-965 */

#define   PANEL_8TO6_DITHER_ENABLE	REG_BIT(3) /* pre-965 */

#define   PFIT_VERT_INTERP_MASK		REG_GENMASK(11, 10) /* pre-965 */

#define   PFIT_VERT_INTERP_BILINEAR	REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)

#define   PFIT_VERT_AUTO_SCALE		REG_BIT(9) /* pre-965 */

#define   PFIT_HORIZ_INTERP_MASK	REG_GENMASK(7, 6) /* pre-965 */

#define   PFIT_HORIZ_INTERP_BILINEAR	REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)

#define   PFIT_HORIZ_AUTO_SCALE		REG_BIT(5) /* pre-965 */

#define   PFIT_PANEL_8TO6_DITHER_ENABLE	REG_BIT(3) /* pre-965 */



#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)

#define   PFIT_VERT_SCALE_MASK		REG_GENMASK(31, 20) /* pre-965 */