Commit e26602be authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Tvrtko Ursulin
Browse files

drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence 



TC voltage swing programming sequence was updated with a new step.

BSpec: 54956
Cc: stable@vger.kernel.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220113174826.50272-1-jose.souza@intel.com


(cherry picked from commit 5ff59ddd)
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent ef3ac015

drivers/gpu/drm/i915/display/intel_ddi.c

+22 −0
Original line number Diff line number Diff line
@@ -1298,6 +1298,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 


		intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),

			     DKL_TX_DP20BITMODE, 0);



		if (IS_ALDERLAKE_P(dev_priv)) {

			u32 val;



			if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

				if (ln == 0) {

					val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);

					val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);

				} else {

					val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);

					val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);

				}

			} else {

				val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);

				val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);

			}



			intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),

				     DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |

				     DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,

				     val);

		}

	}

}

drivers/gpu/drm/i915/i915_reg.h

+6 −2
Original line number Diff line number Diff line
@@ -11167,7 +11167,11 @@ enum skl_power_gate { 
						     _DKL_TX_DPCNTL1)









#define _DKL_TX_DPCNTL2					0x2C8









#define  DKL_TX_DP20BITMODE				(1 << 2)









#define  DKL_TX_DP20BITMODE				REG_BIT(2)









#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK	REG_GENMASK(4, 3)









#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))









#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK	REG_GENMASK(6, 5)









#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))









#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \









						     _DKL_PHY1_BASE, \









						     _DKL_PHY2_BASE) + \