Commit e24f9c5f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_urgent_for_v5.11_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Borislav Petkov:
 "I hope this is the last batch of x86/urgent updates for this round:

   - Remove superfluous EFI PGD range checks which lead to those
     assertions failing with certain kernel configs and LLVM.

   - Disable setting breakpoints on facilities involved in #DB exception
     handling to avoid infinite loops.

   - Add extra serialization to non-serializing MSRs (IA32_TSC_DEADLINE
     and x2 APIC MSRs) to adhere to SDM's recommendation and avoid any
     theoretical issues.

   - Re-add the EPB MSR reading on turbostat so that it works on older
     kernels which don't have the corresponding EPB sysfs file.

   - Add Alder Lake to the list of CPUs which support split lock.

   - Fix %dr6 register handling in order to be able to set watchpoints
     with gdb again.

   - Disable CET instrumentation in the kernel so that gcc doesn't add
     ENDBR64 to kernel code and thus confuse tracing"

* tag 'x86_urgent_for_v5.11_rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/efi: Remove EFI PGD build time checks
  x86/debug: Prevent data breakpoints on cpu_dr7
  x86/debug: Prevent data breakpoints on __per_cpu_offset
  x86/apic: Add extra serialization for non-serializing MSRs
  tools/power/turbostat: Fallback to an MSR read for EPB
  x86/split_lock: Enable the split lock feature on another Alder Lake CPU
  x86/debug: Fix DR6 handling
  x86/build: Disable CET instrumentation in the kernel
parents 2db138bb 816ef8d7

Makefile

+0 −6
Original line number Diff line number Diff line
@@ -949,12 +949,6 @@ KBUILD_CFLAGS += $(call cc-option,-Werror=designated-init) 
# change __FILE__ to the relative path from the srctree

KBUILD_CPPFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)



# ensure -fcf-protection is disabled when using retpoline as it is

# incompatible with -mindirect-branch=thunk-extern

ifdef CONFIG_RETPOLINE

KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none)

endif



# include additional Makefiles when needed

include-y			:= scripts/Makefile.extrawarn

include-$(CONFIG_KASAN)		+= scripts/Makefile.kasan

arch/x86/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -120,6 +120,9 @@ else 


        KBUILD_CFLAGS += -mno-red-zone

        KBUILD_CFLAGS += -mcmodel=kernel



	# Intel CET isn't enabled in the kernel

	KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none)

endif



ifdef CONFIG_X86_X32

arch/x86/include/asm/apic.h

+0 −10
Original line number Diff line number Diff line
@@ -197,16 +197,6 @@ static inline bool apic_needs_pit(void) { return true; } 
#endif /* !CONFIG_X86_LOCAL_APIC */



#ifdef CONFIG_X86_X2APIC

/*

 * Make previous memory operations globally visible before

 * sending the IPI through x2apic wrmsr. We need a serializing instruction or

 * mfence for this.

 */

static inline void x2apic_wrmsr_fence(void)

{

	asm volatile("mfence" : : : "memory");

}



static inline void native_apic_msr_write(u32 reg, u32 v)

{

	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||

arch/x86/include/asm/barrier.h

+18 −0
Original line number Diff line number Diff line
@@ -84,4 +84,22 @@ do { \ 


#include <asm-generic/barrier.h>



/*

 * Make previous memory operations globally visible before

 * a WRMSR.

 *

 * MFENCE makes writes visible, but only affects load/store

 * instructions.  WRMSR is unfortunately not a load/store

 * instruction and is unaffected by MFENCE.  The LFENCE ensures

 * that the WRMSR is not reordered.

 *

 * Most WRMSRs are full serializing instructions themselves and

 * do not require this barrier.  This is only required for the

 * IA32_TSC_DEADLINE and X2APIC MSRs.

 */

static inline void weak_wrmsr_fence(void)

{

	asm volatile("mfence; lfence" : : : "memory");

}



#endif /* _ASM_X86_BARRIER_H */

arch/x86/kernel/apic/apic.c

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#include <asm/perf_event.h>

#include <asm/x86_init.h>

#include <linux/atomic.h>

#include <asm/barrier.h>

#include <asm/mpspec.h>

#include <asm/i8259.h>

#include <asm/proto.h>
@@ -477,6 +478,9 @@ static int lapic_next_deadline(unsigned long delta, 
{

	u64 tsc;



	/* This MSR is special and need a special fence: */

	weak_wrmsr_fence();



	tsc = rdtsc();

	wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));

	return 0;