Commit e24453e1 authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: Initialise bank HW for each a bank 



The mt8195 IOMMU HW max support 5 banks, and regarding the banks'
registers, it looks like:

 ----------------------------------------
 |bank0  | bank1 | bank2 | bank3 | bank4|
 ----------------------------------------
 |global |
 |control|         null
 |regs   |
 -----------------------------------------
 |bank   |bank   |bank   |bank   |bank   |
 |regs   |regs   |regs   |regs   |regs   |
 |       |       |       |       |       |
 -----------------------------------------

Each bank has some special bank registers and it share bank0's global
control registers. this patch initialise the bank hw with the bankid.

In the hw_init, we always initialise bank0's control register since
we don't know if the bank0 is initialised.

Additionally, About each bank's register base, always delta 0x1000.
like bank[x + 1] = bank[x] + 0x1000.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220503071427.2285-31-yong.wu@mediatek.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 99ca0228

drivers/iommu/mtk_iommu.c

+20 −12
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ static void mtk_iommu_unbind(struct device *dev) 


static const struct iommu_ops mtk_iommu_ops;



static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);

static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);



#define MTK_IOMMU_TLB_ADDR(iova) ({					\

	dma_addr_t _addr = iova;					\
@@ -642,12 +642,14 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, 


	mutex_lock(&data->mutex);

	bank = &data->bank[bankid];

	if (!bank->m4u_dom) { /* Initialize the M4U HW */

	if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */

		ret = pm_runtime_resume_and_get(m4udev);

		if (ret < 0)

		if (ret < 0) {

			dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);

			goto err_unlock;

		}



		ret = mtk_iommu_hw_init(data);

		ret = mtk_iommu_hw_init(data, bankid);

		if (ret) {

			pm_runtime_put(m4udev);

			goto err_unlock;
@@ -897,11 +899,16 @@ static const struct iommu_ops mtk_iommu_ops = { 
	}

};



static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)

static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)

{

	const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];

	const struct mtk_iommu_bank_data *bank0 = &data->bank[0];

	u32 regval;



	/*

	 * Global control settings are in bank0. May re-init these global registers

	 * since no sure if there is bank0 consumers.

	 */

	if (data->plat_data->m4u_plat == M4U_MT8173) {

		regval = F_MMU_PREFETCH_RT_REPLACE_MOD |

			 F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
@@ -944,13 +951,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 
	}

	writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);



	/* Independent settings for each bank */

	regval = F_L2_MULIT_HIT_EN |

		F_TABLE_WALK_FAULT_INT_EN |

		F_PREETCH_FIFO_OVERFLOW_INT_EN |

		F_MISS_FIFO_OVERFLOW_INT_EN |

		F_PREFETCH_FIFO_ERR_INT_EN |

		F_MISS_FIFO_ERR_INT_EN;

	writel_relaxed(regval, bank0->base + REG_MMU_INT_CONTROL0);

	writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);



	regval = F_INT_TRANSLATION_FAULT |

		F_INT_MAIN_MULTI_HIT_FAULT |
@@ -959,19 +967,19 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 
		F_INT_TLB_MISS_FAULT |

		F_INT_MISS_TRANSACTION_FIFO_FAULT |

		F_INT_PRETETCH_TRANSATION_FIFO_FAULT;

	writel_relaxed(regval, bank0->base + REG_MMU_INT_MAIN_CONTROL);

	writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);



	if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))

		regval = (data->protect_base >> 1) | (data->enable_4GB << 31);

	else

		regval = lower_32_bits(data->protect_base) |

			 upper_32_bits(data->protect_base);

	writel_relaxed(regval, bank0->base + REG_MMU_IVRP_PADDR);

	writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);



	if (devm_request_irq(bank0->parent_dev, bank0->irq, mtk_iommu_isr, 0,

			     dev_name(bank0->parent_dev), (void *)bank0)) {

		writel_relaxed(0, bank0->base + REG_MMU_PT_BASE_ADDR);

		dev_err(bank0->parent_dev, "Failed @ IRQ-%d Request\n", bank0->irq);

	if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,

			     dev_name(bankx->parent_dev), (void *)bankx)) {

		writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);

		dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);

		return -ENODEV;

	}