Commit e19c33db authored by Ludovic Barre's avatar Ludovic Barre Committed by Ulf Hansson
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dt-bindings: mmc: mmci: add delay block base register for sdmmc 



To support the sdr104 mode, the sdmmc variant has a hardware delay block to
manage the clock phase when sampling data received by the card.

This patch adds a second base register (optional) for sdmmc delay block.

Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200128090636.13689-6-ludovic.barre@st.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 31b963e1

Documentation/devicetree/bindings/mmc/mmci.txt

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ specific for ux500 variant: 
- st,sig-pin-fbclk       : feedback clock signal pin used.



specific for sdmmc variant:

- reg			 : a second base register may be defined if a delay

                           block is present and used for tuning.

- st,sig-dir             : signal direction polarity used for cmd, dat0 dat123.

- st,neg-edge            : data & command phase relation, generated on

                           sd clock falling edge.