Commit e19a0adf authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Lorenzo Pieralisi
Browse files

PCI: cadence: Add support to configure virtual functions 

Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.

Link: https://lore.kernel.org/r/20210819123343.1951-7-kishon@ti.com


Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 0cf985d6

drivers/pci/controller/cadence/pcie-cadence-ep.c

+119 −21
Original line number Diff line number Diff line
@@ -16,11 +16,37 @@ 
#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE		0x1

#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY	0x3



static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn)

{

	u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;

	u32 first_vf_offset, stride;



	if (vfn == 0)

		return fn;



	first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET);

	stride = cdns_pcie_ep_fn_readw(pcie, fn, cap +  PCI_SRIOV_VF_STRIDE);

	fn = fn + first_vf_offset + ((vfn - 1) * stride);



	return fn;

}



static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,

				     struct pci_epf_header *hdr)

{

	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET;

	struct cdns_pcie *pcie = &ep->pcie;

	u32 reg;



	if (vfn > 1) {

		dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n");

		return -EINVAL;

	} else if (vfn == 1) {

		reg = cap + PCI_SRIOV_VF_DID;

		cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid);

		return 0;

	}



	cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);

	cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
@@ -92,21 +118,30 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, 


	addr0 = lower_32_bits(bar_phys);

	addr1 = upper_32_bits(bar_phys);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),

			 addr0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),

			 addr1);



	if (vfn == 1)

		reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);

	else

		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);

	b = (bar < BAR_4) ? bar : bar - BAR_4;



	if (vfn == 0 || vfn == 1) {

		cfg = cdns_pcie_readl(pcie, reg);

		cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |

			 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));

		cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |

			CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));

		cdns_pcie_writel(pcie, reg, cfg);

	}



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),

			 addr0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),

			 addr1);



	if (vfn > 0)

		epf = &epf->epf[vfn - 1];

	epf->epf_bar[bar] = epf_bar;



	return 0;
@@ -121,19 +156,27 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, 
	enum pci_barno bar = epf_bar->barno;

	u32 reg, cfg, b, ctrl;



	if (vfn == 1)

		reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);

	else

		reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);

	b = (bar < BAR_4) ? bar : bar - BAR_4;



	if (vfn == 0 || vfn == 1) {

		ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;

		cfg = cdns_pcie_readl(pcie, reg);

		cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |

			 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));

		cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);

		cdns_pcie_writel(pcie, reg, cfg);

	}



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);



	if (vfn > 0)

		epf = &epf->epf[vfn - 1];

	epf->epf_bar[bar] = NULL;

}
@@ -151,6 +194,7 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, 
		return -EINVAL;

	}



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);

	cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size);



	set_bit(r, &ep->ob_region_map);
@@ -186,6 +230,8 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) 
	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;

	u16 flags;



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	/*

	 * Set the Multiple Message Capable bitfield into the Message Control

	 * register.
@@ -206,6 +252,8 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) 
	u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;

	u16 flags, mme;



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	/* Validate that the MSI feature is actually enabled. */

	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);

	if (!(flags & PCI_MSI_FLAGS_ENABLE))
@@ -227,6 +275,8 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) 
	u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;

	u32 val, reg;



	func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no);



	reg = cap + PCI_MSIX_FLAGS;

	val = cdns_pcie_ep_fn_readw(pcie, func_no, reg);

	if (!(val & PCI_MSIX_FLAGS_ENABLE))
@@ -246,6 +296,8 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, 
	u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;

	u32 val, reg;



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	reg = cap + PCI_MSIX_FLAGS;

	val = cdns_pcie_ep_fn_readw(pcie, fn, reg);

	val &= ~PCI_MSIX_FLAGS_QSIZE;
@@ -265,8 +317,8 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, 
	return 0;

}



static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,

				     u8 intx, bool is_asserted)

static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx,

				     bool is_asserted)

{

	struct cdns_pcie *pcie = &ep->pcie;

	unsigned long flags;
@@ -335,6 +387,8 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 
	u8 msi_count;

	u64 pci_addr, pci_addr_mask = 0xff;



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	/* Check whether the MSI feature has been enabled by the PCI host. */

	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);

	if (!(flags & PCI_MSI_FLAGS_ENABLE))
@@ -388,6 +442,8 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, 
	int ret;

	int i;



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	/* Check whether the MSI feature has been enabled by the PCI host. */

	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);

	if (!(flags & PCI_MSI_FLAGS_ENABLE))
@@ -438,6 +494,12 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 
	u16 flags;

	u8 bir;



	epf = &ep->epf[fn];

	if (vfn > 0)

		epf = &epf->epf[vfn - 1];



	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);



	/* Check whether the MSI-X feature has been enabled by the PCI host. */

	flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS);

	if (!(flags & PCI_MSIX_FLAGS_ENABLE))
@@ -448,7 +510,6 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, 
	bir = tbl_offset & PCI_MSIX_TABLE_BIR;

	tbl_offset &= PCI_MSIX_TABLE_OFFSET;



	epf = &ep->epf[fn];

	msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;

	msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;

	msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
@@ -475,9 +536,15 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, 
				  u16 interrupt_num)

{

	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	struct cdns_pcie *pcie = &ep->pcie;

	struct device *dev = pcie->dev;



	switch (type) {

	case PCI_EPC_IRQ_LEGACY:

		if (vfn > 0) {

			dev_err(dev, "Cannot raise legacy interrupts for VF\n");

			return -EINVAL;

		}

		return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);



	case PCI_EPC_IRQ_MSI:
@@ -515,6 +582,13 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) 
	return 0;

}



static const struct pci_epc_features cdns_pcie_epc_vf_features = {

	.linkup_notifier = false,

	.msi_capable = true,

	.msix_capable = true,

	.align = 65536,

};



static const struct pci_epc_features cdns_pcie_epc_features = {

	.linkup_notifier = false,

	.msi_capable = true,
@@ -525,7 +599,10 @@ static const struct pci_epc_features cdns_pcie_epc_features = { 
static const struct pci_epc_features*

cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)

{

	if (!vfunc_no)

		return &cdns_pcie_epc_features;



	return &cdns_pcie_epc_vf_features;

}



static const struct pci_epc_ops cdns_pcie_epc_ops = {
@@ -551,9 +628,11 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 
	struct platform_device *pdev = to_platform_device(dev);

	struct device_node *np = dev->of_node;

	struct cdns_pcie *pcie = &ep->pcie;

	struct cdns_pcie_epf *epf;

	struct resource *res;

	struct pci_epc *epc;

	int ret;

	int i;



	pcie->is_rc = false;
@@ -598,6 +677,25 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 
	if (!ep->epf)

		return -ENOMEM;



	epc->max_vfs = devm_kcalloc(dev, epc->max_functions,

				    sizeof(*epc->max_vfs), GFP_KERNEL);

	if (!epc->max_vfs)

		return -ENOMEM;



	ret = of_property_read_u8_array(np, "max-virtual-functions",

					epc->max_vfs, epc->max_functions);

	if (ret == 0) {

		for (i = 0; i < epc->max_functions; i++) {

			epf = &ep->epf[i];

			if (epc->max_vfs[i] == 0)

				continue;

			epf->epf = devm_kcalloc(dev, epc->max_vfs[i],

						sizeof(*ep->epf), GFP_KERNEL);

			if (!epf->epf)

				return -ENOMEM;

		}

	}



	ret = pci_epc_mem_init(epc, pcie->mem_res->start,

			       resource_size(pcie->mem_res), PAGE_SIZE);

	if (ret < 0) {

drivers/pci/controller/cadence/pcie-cadence.h

+9 −0
Original line number Diff line number Diff line
@@ -53,6 +53,12 @@ 
	(CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)

#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \

	(CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)

#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \

	(((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn))

#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \

	(CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008)

#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \

	(CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008)

#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \

	(GENMASK(4, 0) << ((b) * 8))

#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
@@ -117,6 +123,7 @@ 


#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET	0x90

#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET	0xb0

#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET	0x200



/*

 * Root Port Registers (PCI configuration space for the root port function)
@@ -311,9 +318,11 @@ struct cdns_pcie_rc { 


/**

 * struct cdns_pcie_epf - Structure to hold info about endpoint function

 * @epf: Info about virtual functions attached to the physical function

 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers

 */

struct cdns_pcie_epf {

	struct cdns_pcie_epf *epf;

	struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];

};