Commit e0fb12c6 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 updates for Linux 6.6

- Add support for TLB range invalidation of Stage-2 page tables,
  avoiding unnecessary invalidations. Systems that do not implement
  range invalidation still rely on a full invalidation when dealing
  with large ranges.

- Add infrastructure for forwarding traps taken from a L2 guest to
  the L1 guest, with L0 acting as the dispatcher, another baby step
  towards the full nested support.

- Simplify the way we deal with the (long deprecated) 'CPU target',
  resulting in a much needed cleanup.

- Fix another set of PMU bugs, both on the guest and host sides,
  as we seem to never have any shortage of those...

- Relax the alignment requirements of EL2 VA allocations for
  non-stack allocations, as we were otherwise wasting a lot of that
  precious VA space.

- The usual set of non-functional cleanups, although I note the lack
  of spelling fixes...
parents 2dde18cd 1f66f124

arch/arm/include/asm/arm_pmuv3.h

+2 −0
Original line number Diff line number Diff line
@@ -227,6 +227,8 @@ static inline bool kvm_set_pmuserenr(u64 val) 
	return false;

}



static inline void kvm_vcpu_pmu_resync_el0(void) {}



/* PMU Version in DFR Register */

#define ARMV8_PMU_DFR_VER_NI        0

#define ARMV8_PMU_DFR_VER_V3P4      0x5

arch/arm64/include/asm/kvm_arm.h

+50 −1
Original line number Diff line number Diff line
@@ -18,10 +18,19 @@ 
#define HCR_DCT		(UL(1) << 57)

#define HCR_ATA_SHIFT	56

#define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)

#define HCR_TTLBOS	(UL(1) << 55)

#define HCR_TTLBIS	(UL(1) << 54)

#define HCR_ENSCXT	(UL(1) << 53)

#define HCR_TOCU	(UL(1) << 52)

#define HCR_AMVOFFEN	(UL(1) << 51)

#define HCR_TICAB	(UL(1) << 50)

#define HCR_TID4	(UL(1) << 49)

#define HCR_FIEN	(UL(1) << 47)

#define HCR_FWB		(UL(1) << 46)

#define HCR_NV2		(UL(1) << 45)

#define HCR_AT		(UL(1) << 44)

#define HCR_NV1		(UL(1) << 43)

#define HCR_NV		(UL(1) << 42)

#define HCR_API		(UL(1) << 41)

#define HCR_APK		(UL(1) << 40)

#define HCR_TEA		(UL(1) << 37)
@@ -89,7 +98,6 @@ 
			 HCR_BSU_IS | HCR_FB | HCR_TACR | \

			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \

			 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3)

#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)

#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)

#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)

#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
@@ -324,6 +332,47 @@ 
				 BIT(18) |		\

				 GENMASK(16, 15))



/*

 * FGT register definitions

 *

 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.

 * We're not using the generated masks as they are usually ahead of

 * the published ARM ARM, which we use as a reference.

 *

 * Once we get to a point where the two describe the same thing, we'll

 * merge the definitions. One day.

 */

#define __HFGRTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51))

#define __HFGRTR_EL2_MASK	GENMASK(49, 0)

#define __HFGRTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))



#define __HFGWTR_EL2_RES0	(GENMASK(63, 56) | GENMASK(53, 51) |	\

				 BIT(46) | BIT(42) | BIT(40) | BIT(28) | \

				 GENMASK(26, 25) | BIT(21) | BIT(18) |	\

				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))

#define __HFGWTR_EL2_MASK	GENMASK(49, 0)

#define __HFGWTR_EL2_nMASK	(GENMASK(55, 54) | BIT(50))



#define __HFGITR_EL2_RES0	GENMASK(63, 57)

#define __HFGITR_EL2_MASK	GENMASK(54, 0)

#define __HFGITR_EL2_nMASK	GENMASK(56, 55)



#define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\

				 GENMASK(21, 20) | BIT(8))

#define __HDFGRTR_EL2_MASK	~__HDFGRTR_EL2_nMASK

#define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)



#define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \

				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \

				 BIT(22) | BIT(9) | BIT(6))

#define __HDFGWTR_EL2_MASK	~__HDFGWTR_EL2_nMASK

#define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)



/* Similar definitions for HCRX_EL2 */

#define __HCRX_EL2_RES0		(GENMASK(63, 16) | GENMASK(13, 12))

#define __HCRX_EL2_MASK		(0)

#define __HCRX_EL2_nMASK	(GENMASK(15, 14) | GENMASK(4, 0))



/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */

#define HPFAR_MASK	(~UL(0xf))

/*

arch/arm64/include/asm/kvm_asm.h

+3 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ enum __kvm_host_smccc_func { 
	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa,

	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_ipa_nsh,

	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid,

	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range,

	__KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context,

	__KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff,

	__KVM_HOST_SMCCC_FUNC___vgic_v3_read_vmcr,
@@ -229,6 +230,8 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, phys_addr_t ipa, 
extern void __kvm_tlb_flush_vmid_ipa_nsh(struct kvm_s2_mmu *mmu,

					 phys_addr_t ipa,

					 int level);

extern void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,

					phys_addr_t start, unsigned long pages);

extern void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu);



extern void __kvm_timer_set_cntvoff(u64 cntvoff);

arch/arm64/include/asm/kvm_host.h

+15 −9
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#define KVM_REQ_RELOAD_GICv4	KVM_ARCH_REQ(4)

#define KVM_REQ_RELOAD_PMU	KVM_ARCH_REQ(5)

#define KVM_REQ_SUSPEND		KVM_ARCH_REQ(6)

#define KVM_REQ_RESYNC_PMU_EL0	KVM_ARCH_REQ(7)



#define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \

				     KVM_DIRTY_LOG_INITIALLY_SET)
@@ -380,6 +381,7 @@ enum vcpu_sysreg { 
	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */

	HSTR_EL2,	/* Hypervisor System Trap Register */

	HACR_EL2,	/* Hypervisor Auxiliary Control Register */

	HCRX_EL2,	/* Extended Hypervisor Configuration Register */

	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */

	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */

	TCR_EL2,	/* Translation Control Register (EL2) */
@@ -400,6 +402,11 @@ enum vcpu_sysreg { 
	TPIDR_EL2,	/* EL2 Software Thread ID Register */

	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */

	SP_EL2,		/* EL2 Stack Pointer */

	HFGRTR_EL2,

	HFGWTR_EL2,

	HFGITR_EL2,

	HDFGRTR_EL2,

	HDFGWTR_EL2,

	CNTHP_CTL_EL2,

	CNTHP_CVAL_EL2,

	CNTHV_CTL_EL2,
@@ -567,8 +574,7 @@ struct kvm_vcpu_arch { 
	/* Cache some mmu pages needed inside spinlock regions */

	struct kvm_mmu_memory_cache mmu_page_cache;



	/* Target CPU and feature flags */

	int target;

	/* feature flags */

	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);



	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
@@ -669,6 +675,8 @@ struct kvm_vcpu_arch { 
#define VCPU_SVE_FINALIZED	__vcpu_single_flag(cflags, BIT(1))

/* PTRAUTH exposed to guest */

#define GUEST_HAS_PTRAUTH	__vcpu_single_flag(cflags, BIT(2))

/* KVM_ARM_VCPU_INIT completed */

#define VCPU_INITIALIZED	__vcpu_single_flag(cflags, BIT(3))



/* Exception pending */

#define PENDING_EXCEPTION	__vcpu_single_flag(iflags, BIT(0))
@@ -899,7 +907,6 @@ struct kvm_vcpu_stat { 
	u64 exits;

};



void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);

unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);

int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);

int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
@@ -967,8 +974,6 @@ void kvm_arm_resume_guest(struct kvm *kvm); 
#define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)

#endif /* __KVM_NVHE_HYPERVISOR__ */



void force_vm_exit(const cpumask_t *mask);



int handle_exit(struct kvm_vcpu *vcpu, int exception_index);

void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
@@ -983,6 +988,7 @@ int kvm_handle_cp10_id(struct kvm_vcpu *vcpu); 
void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);



int __init kvm_sys_reg_table_init(void);

int __init populate_nv_trap_config(void);



bool lock_all_vcpus(struct kvm *kvm);

void unlock_all_vcpus(struct kvm *kvm);
@@ -1049,8 +1055,6 @@ static inline bool kvm_system_needs_idmapped_vectors(void) 
	return cpus_have_const_cap(ARM64_SPECTRE_V3A);

}



void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);



static inline void kvm_arch_sync_events(struct kvm *kvm) {}

static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
@@ -1113,13 +1117,15 @@ int __init kvm_set_ipa_limit(void); 
#define __KVM_HAVE_ARCH_VM_ALLOC

struct kvm *kvm_arch_alloc_vm(void);



#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS



#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE



static inline bool kvm_vm_is_protected(struct kvm *kvm)

{

	return false;

}



void kvm_init_protected_traps(struct kvm_vcpu *vcpu);



int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);

bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/kvm_mmu.h

+1 −0
Original line number Diff line number Diff line
@@ -168,6 +168,7 @@ int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size, 
			   void __iomem **haddr);

int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,

			     void **haddr);

int create_hyp_stack(phys_addr_t phys_addr, unsigned long *haddr);

void __init free_hyp_pgds(void);



void stage2_unmap_vm(struct kvm *kvm);