Commit e0f72db3 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Jakub Kicinski
Browse files

net: ethernet: ti: am65-cpsw: Add support for SGMII mode 



Add support for configuring the CPSW Ethernet Switch in SGMII mode.

Depending on the SoC, allow selecting SGMII mode as a supported interface,
based on the compatible used.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a2935a1c

drivers/net/ethernet/ti/am65-cpsw-nuss.c

+10 −1
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C



#define AM65_CPSW_SGMII_CONTROL_REG		0x010

#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG	0x018

#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)



#define AM65_CPSW_CTL_VLAN_AWARE		BIT(1)
@@ -1496,10 +1497,15 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in 
	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);

	struct am65_cpsw_common *common = port->common;



	if (common->pdata.extra_modes & BIT(state->interface))

	if (common->pdata.extra_modes & BIT(state->interface)) {

		if (state->interface == PHY_INTERFACE_MODE_SGMII)

			writel(ADVERTISE_SGMII,

			       port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);



		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,

		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

	}

}



static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,

					 phy_interface_t interface)
@@ -1539,6 +1545,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy 


	if (speed == SPEED_1000)

		mac_control |= CPSW_SL_CTL_GIG;

	if (interface == PHY_INTERFACE_MODE_SGMII)

		mac_control |= CPSW_SL_CTL_EXT_EN;

	if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface))

		/* Can be used with in band mode only */

		mac_control |= CPSW_SL_CTL_EXT_EN;
@@ -2157,6 +2165,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 
		break;



	case PHY_INTERFACE_MODE_QSGMII:

	case PHY_INTERFACE_MODE_SGMII:

		if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {

			__set_bit(port->slave.phy_if,

				  port->slave.phylink_config.supported_interfaces);