Commit e0ada51d authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 



Conflicts were simple overlapping changes in microchip
driver.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0638eb57 83beed7b

.gitignore

+3 −4
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#

.*

*.a

*.asn1.[ch]

*.bin

*.bz2

*.c.[012]*.*
@@ -22,6 +23,7 @@ 
*.gz

*.i

*.ko

*.lex.c

*.ll

*.lst

*.lz4
@@ -37,6 +39,7 @@ 
*.so.dbg

*.su

*.symtypes

*.tab.[ch]

*.tar

*.xz

Module.symvers
@@ -129,7 +132,3 @@ all.config 


# Kdevelop4

*.kdev4
 


#Automatically generated by ASN.1 compiler

net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c

net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h

Documentation/clk.txt

+13 −3
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@@ -268,9 +268,19 @@ The common clock framework uses two global locks, the prepare lock and the 
enable lock.



The enable lock is a spinlock and is held across calls to the .enable,

.disable and .is_enabled operations. Those operations are thus not allowed to

sleep, and calls to the clk_enable(), clk_disable() and clk_is_enabled() API

functions are allowed in atomic context.

.disable operations. Those operations are thus not allowed to sleep,

and calls to the clk_enable(), clk_disable() API functions are allowed in

atomic context.



For clk_is_enabled() API, it is also designed to be allowed to be used in

atomic context. However, it doesn't really make any sense to hold the enable

lock in core, unless you want to do something else with the information of

the enable state with that lock held. Otherwise, seeing if a clk is enabled is

a one-shot read of the enabled state, which could just as easily change after

the function returns because the lock is released. Thus the user of this API

needs to handle synchronizing the read of the state with whatever they're

using it for to make sure that the enable state doesn't change during that

time.



The prepare lock is a mutex and is held across calls to all other operations.

All those operations are allowed to sleep, and calls to the corresponding API

Documentation/core-api/kernel-api.rst

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@@ -136,6 +136,19 @@ Sorting 
.. kernel-doc:: lib/list_sort.c

   :export:



Text Searching

--------------



.. kernel-doc:: lib/textsearch.c

   :doc: ts_intro



.. kernel-doc:: lib/textsearch.c

   :export:



.. kernel-doc:: include/linux/textsearch.h

   :functions: textsearch_find textsearch_next \

               textsearch_get_pattern textsearch_get_pattern_len



UUID/GUID

---------

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

+15 −5
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@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system. 
Required Properties:



- compatible: Should be one of:

	- "mediatek,mt2701-audsys", "syscon"

	- "mediatek,mt7622-audsys", "syscon"

- #clock-cells: Must be 1
@@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from 
Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Required sub-nodes:

-------

For common binding part and usage, refer to

../sonud/mt2701-afe-pcm.txt.



Example:



audsys: audsys@11220000 {

	audsys: clock-controller@11220000 {

		compatible = "mediatek,mt7622-audsys", "syscon";

	reg = <0 0x11220000 0 0x1000>;

		reg = <0 0x11220000 0 0x2000>;

		#clock-cells = <1>;



		afe: audio-controller {

			...

		};

	};

Documentation/devicetree/bindings/clock/imx6sll-clock.txt

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* Clock bindings for Freescale i.MX6 SLL



Required properties:

- compatible: Should be "fsl,imx6sll-ccm"

- reg: Address and length of the register set

- #clock-cells: Should be <1>

- clocks: list of clock specifiers, must contain an entry for each required

  entry in clock-names

- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sll-clock.h

for the full list of i.MX6 SLL clock IDs.



Examples:



#include <dt-bindings/clock/imx6sll-clock.h>



clks: clock-controller@20c4000 {

		compatible = "fsl,imx6sll-ccm";

		reg = <0x020c4000 0x4000>;

		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;

		#clock-cells = <1>;

		clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;

		clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";

};



uart1: serial@2020000 {

		compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";

		reg = <0x02020000 0x4000>;

		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks IMX6SLL_CLK_UART1_IPG>,

			 <&clks IMX6SLL_CLK_UART1_SERIAL>;

		clock-names = "ipg", "per";

};