Unverified Commit e0a00cd6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!3123 Add pcie acs and no-bus-reset quirk for mucse Nics 

Merge Pull Request from: @guhuiguang 
 
1. Some MUCSE N10/N400 chips do not support bus/hot reset.  The PCIE automatically disables LTSSM when Secondary Bus Reset is received and the device stops working.  Prevent bus reset for these devices.

2. Some MUCSE N10/N400 chips  may be multi-function devices, but the hardware does not advertise ACS capability. Add an ACS quirk for these chips NICS so the functions can be in independent IOMMU groups. 
 
Link:https://gitee.com/openeuler/kernel/pulls/3123

 

Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 367ac46f 8a6f0cbf

drivers/pci/quirks.c

+35 −0
Original line number Diff line number Diff line
@@ -3642,6 +3642,26 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 
 */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);



/*

 * Some MUCSE N10/N400 chips do not support bus/hot reset.  The PCIESS

 * automatically disables LTSSM when Secondary Bus Reset is received and

 * the device stops working.  Prevent bus reset for these devices.

 */

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1000, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c00, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1020, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c20, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1060, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c00, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1001, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c01, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1003, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c03, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1021, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c00, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1061, quirk_no_bus_reset);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MUCSE, 0x1c61, quirk_no_bus_reset);



static void quirk_no_pm_reset(struct pci_dev *dev)

{

	/*
@@ -5003,6 +5023,21 @@ static const struct pci_dev_acs_enabled { 
	/* because rootcomplex Vendor id is 0x17cd on phytium cpu */

	{ 0x17cd, PCI_ANY_ID, pci_quirk_xgene_acs },

#endif

	/* Mucse multi-function devices */

	{ PCI_VENDOR_ID_MUCSE, 0x1000, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c00, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1020, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c20, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1060, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c60, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1001, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c01, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1003, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c03, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1021, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c21, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1061, pci_quirk_mf_endpoint_acs },

	{ PCI_VENDOR_ID_MUCSE, 0x1c61, pci_quirk_mf_endpoint_acs },

	{ 0 }

};

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -3043,6 +3043,8 @@ 
#define PCI_DEVICE_ID_INTEL_VMD_9A0B	0x9a0b

#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152



#define PCI_VENDOR_ID_MUCSE		0x8848



#define PCI_VENDOR_ID_WANGXUN		0x8088



#define PCI_VENDOR_ID_SCALEMP		0x8686