Commit e09be87a authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Daniel Vetter
Browse files

drm/i915/guc: Early initialization of GuC send registers 



Base offset and count of the GuC scratch registers, used for
sending MMIO messages to GuC, can be initialized earlier with
other GuC members that also depends on platform.

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20210603051630.2635-20-matthew.brost@intel.com
parent 8d99e09c

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+9 −9
Original line number Diff line number Diff line
@@ -60,15 +60,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc) 
	enum forcewake_domains fw_domains = 0;

	unsigned int i;



	if (INTEL_GEN(gt->i915) >= 11) {

		guc->send_regs.base =

				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));

		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;

	} else {

		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;

		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);

	}

	GEM_BUG_ON(!guc->send_regs.base);

	GEM_BUG_ON(!guc->send_regs.count);



	for (i = 0; i < guc->send_regs.count; i++) {

		fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
@@ -172,11 +165,18 @@ void intel_guc_init_early(struct intel_guc *guc) 
		guc->interrupts.reset = gen11_reset_guc_interrupts;

		guc->interrupts.enable = gen11_enable_guc_interrupts;

		guc->interrupts.disable = gen11_disable_guc_interrupts;

		guc->send_regs.base =

			i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));

		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;



	} else {

		guc->notify_reg = GUC_SEND_INTERRUPT;

		guc->interrupts.reset = gen9_reset_guc_interrupts;

		guc->interrupts.enable = gen9_enable_guc_interrupts;

		guc->interrupts.disable = gen9_disable_guc_interrupts;

		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;

		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);

	}

}