Commit e06f1c60 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/dsi: Extract {vlv,bxt}_get_pclk() 



Extract the state->freq computation for VLV/BXT DSI PLL
into small helpers. We want to use these during the state
computation as well.

Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-5-ville.syrjala@linux.intel.com
parent 9988db59

drivers/gpu/drm/i915/display/vlv_dsi_pll.c

+68 −53
Original line number Diff line number Diff line
@@ -113,6 +113,61 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 
	return 0;

}



static int vlv_dsi_pclk(struct intel_encoder *encoder,

			struct intel_crtc_state *config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	u32 dsi_clock;

	u32 pll_ctl, pll_div;

	u32 m = 0, p = 0, n;

	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;

	int i;



	pll_ctl = config->dsi_pll.ctrl;

	pll_div = config->dsi_pll.div;



	/* mask out other bits and extract the P1 divisor */

	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;

	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);



	/* N1 divisor */

	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;

	n = 1 << n; /* register has log2(N1) */



	/* mask out the other bits and extract the M1 divisor */

	pll_div &= DSI_PLL_M1_DIV_MASK;

	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;



	while (pll_ctl) {

		pll_ctl = pll_ctl >> 1;

		p++;

	}

	p--;



	if (!p) {

		drm_err(&dev_priv->drm, "wrong P1 divisor\n");

		return 0;

	}



	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {

		if (lfsr_converts[i] == pll_div)

			break;

	}



	if (i == ARRAY_SIZE(lfsr_converts)) {

		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");

		return 0;

	}



	m = i + 62;



	dsi_clock = (m * refclk) / (p * n);



	return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);

}



/*

 * XXX: The muxing and gating is hard coded for now. Need to add support for

 * sharing PLLs with two DSI outputs.
@@ -262,13 +317,7 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 
		     struct intel_crtc_state *config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	u32 dsi_clock, pclk;

	u32 pll_ctl, pll_div;

	u32 m = 0, p = 0, n;

	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;

	int i;



	drm_dbg_kms(&dev_priv->drm, "\n");
@@ -280,65 +329,31 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 
	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;

	config->dsi_pll.div = pll_div;



	/* mask out other bits and extract the P1 divisor */

	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;

	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);



	/* N1 divisor */

	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;

	n = 1 << n; /* register has log2(N1) */



	/* mask out the other bits and extract the M1 divisor */

	pll_div &= DSI_PLL_M1_DIV_MASK;

	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;



	while (pll_ctl) {

		pll_ctl = pll_ctl >> 1;

		p++;

	}

	p--;



	if (!p) {

		drm_err(&dev_priv->drm, "wrong P1 divisor\n");

		return 0;

	}



	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {

		if (lfsr_converts[i] == pll_div)

			break;

	}



	if (i == ARRAY_SIZE(lfsr_converts)) {

		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");

		return 0;

	return vlv_dsi_pclk(encoder, config);

}



	m = i + 62;



	dsi_clock = (m * refclk) / (p * n);

static int bxt_dsi_pclk(struct intel_encoder *encoder,

			const struct intel_crtc_state *config)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	u32 dsi_ratio, dsi_clk;



	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);

	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;



	return pclk;

	return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);

}



u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,

		     struct intel_crtc_state *config)

{

	u32 pclk;

	u32 dsi_clk;

	u32 dsi_ratio;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);

	u32 pclk;



	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);



	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;



	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;



	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);

	pclk = bxt_dsi_pclk(encoder, config);



	drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);

	return pclk;