Merge tag 'counter-updates-for-6.5a' of...

			counter does not freeze at the boundary points, but

			counts continuously throughout.

		interrupt on terminal count:

			The output signal is initially low, and will remain low

			until the counter reaches zero. The output signal then

			goes high and remains high until a new preset value is

			set.

		hardware retriggerable one-shot:

			The output signal is initially high. The output signal

			will go low by a trigger input signal, and will remain

			low until the counter reaches zero. The output will then

			go high and remain high until the next trigger. A

			trigger results in loading the counter to the preset

			value and setting the output signal low, thus starting

			the one-shot pulse.

		rate generator:

			The output signal is initially high. When the counter

			has decremented to 1, the output signal goes low for one

			clock pulse. The output signal then goes high again, the

			counter is reloaded to the preset value, and the process

			repeats in a periodic manner as such.

		square wave mode:

			The output signal is initially high.

			If the initial count is even, the counter is decremented

			by two on succeeding clock pulses. When the count

			expires, the output signal changes value and the

			counter is reloaded to the preset value. The process

			repeats in periodic manner as such.

			If the initial count is odd, the initial count minus one

			(an even number) is loaded and then is decremented by

			two on succeeding clock pulses. One clock pulse after

			the count expires, the output signal goes low and the

			counter is reloaded to the preset value minus one.

			Succeeding clock pulses decrement the count by two. When

			the count expires, the output goes high again and the

			counter is reloaded to the preset value minus one. The

			process repeats in a periodic manner as such.

		software triggered strobe:

			The output signal is initially high. When the count

			expires, the output will go low for one clock pulse and

			then go high again. The counting sequence is "triggered"

			by setting the preset value.

		hardware triggered strobe:

			The output signal is initially high. Counting is started

			by a trigger input signal. When the count expires, the

			output signal will go low for one clock pulse and then

			go high again. A trigger results in loading the counter

			to the preset value.

What:		/sys/bus/counter/devices/counterX/countY/count_mode_available

What:		/sys/bus/counter/devices/counterX/countY/error_noise_available

What:		/sys/bus/counter/devices/counterX/countY/function_available

S:	Maintained

F:	drivers/video/fbdev/i810/

INTEL 8254 COUNTER DRIVER

M:	William Breathitt Gray <william.gray@linaro.org>

L:	linux-iio@vger.kernel.org

S:	Maintained

F:	drivers/counter/i8254.c

F:	include/linux/i8254.h

INTEL 8255 GPIO DRIVER

M:	William Breathitt Gray <william.gray@linaro.org>

L:	linux-gpio@vger.kernel.org

	  interface. You only need to enable this, if you also want to enable

	  one or more of the counter device drivers below.

config I8254

	tristate

	select COUNTER

	select REGMAP

	help

	  Enables support for the i8254 interface library functions. The i8254

	  interface library provides functions to facilitate communication with

	  interfaces compatible with the venerable Intel 8254 Programmable

	  Interval Timer (PIT). The Intel 825x family of chips was first

	  released in the early 1980s but compatible interfaces are nowadays

	  typically found embedded in larger VLSI processing chips and FPGA

	  components.

	  If built as a module its name will be i8254.

if COUNTER

config 104_QUAD_8

	depends on (PC104 && X86) || COMPILE_TEST

	depends on HAS_IOPORT_MAP

	select ISA_BUS_API

	select REGMAP_MMIO

	help

	  Say yes here to build support for the ACCES 104-QUAD-8 quadrature

	  encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).

	  A counter's respective error flag may be cleared by performing a write

	  operation on the respective count value attribute. Although the

	  104-QUAD-8 counters have a 25-bit range, only the lower 24 bits may be

	  set, either directly or via the counter's preset attribute.

	  operation on the respective count value attribute. The 104-QUAD-8

	  counters may be set either directly or via the counter's preset

	  attribute.

	  The base port addresses for the devices may be configured via the base

	  array module parameter. The interrupt line numbers for the devices may

obj-$(CONFIG_COUNTER) += counter.o

counter-y := counter-core.o counter-sysfs.o counter-chrdev.o

obj-$(CONFIG_I8254)		+= i8254.o

obj-$(CONFIG_104_QUAD_8)	+= 104-quad-8.o

obj-$(CONFIG_INTERRUPT_CNT)		+= interrupt-cnt.o

obj-$(CONFIG_RZ_MTU3_CNT)	+= rz-mtu3-cnt.o