Unverified Commit e02d5c43 authored by Dave Stevenson's avatar Dave Stevenson Committed by Maxime Ripard
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drm/vc4: dsi: Correct DSI register definition 



The DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register
definitions were swapped, so trying to use more than a single data
lane failed as lane 1 would get powered down.
(In theory a 4 lane device would work as all lanes would remain
powered).

Correct the definitions.

Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-3-maxime@cerno.tech
parent 51f4fcd9

drivers/gpu/drm/vc4/vc4_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -306,11 +306,11 @@ 
# define DSI0_PHY_AFEC0_RESET			BIT(11)

# define DSI1_PHY_AFEC0_PD_BG			BIT(11)

# define DSI0_PHY_AFEC0_PD			BIT(10)

# define DSI1_PHY_AFEC0_PD_DLANE3		BIT(10)

# define DSI1_PHY_AFEC0_PD_DLANE1		BIT(10)

# define DSI0_PHY_AFEC0_PD_BG			BIT(9)

# define DSI1_PHY_AFEC0_PD_DLANE2		BIT(9)

# define DSI0_PHY_AFEC0_PD_DLANE1		BIT(8)

# define DSI1_PHY_AFEC0_PD_DLANE1		BIT(8)

# define DSI1_PHY_AFEC0_PD_DLANE3		BIT(8)

# define DSI_PHY_AFEC0_PTATADJ_MASK		VC4_MASK(7, 4)

# define DSI_PHY_AFEC0_PTATADJ_SHIFT		4

# define DSI_PHY_AFEC0_CTATADJ_MASK		VC4_MASK(3, 0)