Commit e022620b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "A bumper crop of arm64 fixes for -rc3.

  The largest change is fixing our parsing of the 'rodata=full' command
  line option, which kstrtobool() started treating as 'rodata=false'.
  The fix actually makes the parsing of that option much less fragile
  and updates the documentation at the same time.

  We still have a boot issue pending when KASLR is disabled at compile
  time, but there's a fresh fix on the list which I'll send next week if
  it holds up to testing.

  Summary:

   - Fix workaround for Cortex-A76 erratum #1286807

   - Add workaround for AMU erratum #2457168 on Cortex-A510

   - Drop reference to removed CONFIG_ARCH_RANDOM #define

   - Fix parsing of the "rodata=full" cmdline option

   - Fix a bunch of issues in the SME register state switching and sigframe code

   - Fix incorrect extraction of the CTR_EL0.CWG register field

   - Fix ACPI cache topology probing when the PPTT is not present

   - Trivial comment and whitespace fixes"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/sme: Don't flush SVE register state when handling SME traps
  arm64/sme: Don't flush SVE register state when allocating SME storage
  arm64/signal: Flush FPSIMD register state when disabling streaming mode
  arm64/signal: Raise limit on stack frames
  arm64/cache: Fix cache_type_cwg() for register generation
  arm64/sysreg: Guard SYS_FIELD_ macros for asm
  arm64/sysreg: Directly include bitfield.h
  arm64: cacheinfo: Fix incorrect assignment of signed error value to unsigned fw_level
  arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly
  arm64: fix rodata=full
  arm64: Fix comment typo
  docs/arm64: elf_hwcaps: unify newlines in HWCAP lists
  arm64: adjust KASLR relocation after ARCH_RANDOM removal
  arm64: Fix match_list for erratum 1286807 on Arm Cortex-A76
parents 012bd7e8 714f3cbd

Documentation/admin-guide/kernel-parameters.txt

+2 −0
Original line number Diff line number Diff line
@@ -5331,6 +5331,8 @@ 
	rodata=		[KNL]

		on	Mark read-only kernel memory as read-only (default).

		off	Leave read-only kernel memory writable for debugging.

		full	Mark read-only kernel memory and aliases as read-only

		        [arm64]



	rockchip.usb_uart

			Enable the uart passthrough on the designated usb port

Documentation/arm64/elf_hwcaps.rst

+0 −10
Original line number Diff line number Diff line
@@ -242,44 +242,34 @@ HWCAP2_MTE3 
    by Documentation/arm64/memory-tagging-extension.rst.



HWCAP2_SME



    Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described

    by Documentation/arm64/sme.rst.



HWCAP2_SME_I16I64



    Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.



HWCAP2_SME_F64F64



    Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.



HWCAP2_SME_I8I32



    Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.



HWCAP2_SME_F16F32



    Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.



HWCAP2_SME_B16F32



    Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.



HWCAP2_SME_F32F32



    Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.



HWCAP2_SME_FA64



    Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.



HWCAP2_WFXT



    Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.



HWCAP2_EBF16



    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.



4. Unused AT_HWCAP bits

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ stable kernels. 
| Allwinner      | A64/R18         | UNKNOWN1        | SUN50I_ERRATUM_UNKNOWN1     |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2457168        | ARM64_ERRATUM_2457168       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2038923        | ARM64_ERRATUM_2038923       |

arch/arm64/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -917,6 +917,23 @@ config ARM64_ERRATUM_1902691 


	  If unsure, say Y.



config ARM64_ERRATUM_2457168

	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"

	depends on ARM64_AMU_EXTN

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.



	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate

	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments

	  incorrectly giving a significantly higher output value.



	  Work around this problem by returning 0 when reading the affected counter in

	  key locations that results in disabling all users of this counter. This effect

	  is the same to firmware disabling affected counters.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static __always_inline int icache_is_vpipt(void) 


static inline u32 cache_type_cwg(void)

{

	return (read_cpuid_cachetype() >> CTR_EL0_CWG_SHIFT) & CTR_EL0_CWG_MASK;

	return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());

}



#define __read_mostly __section(".data..read_mostly")