Commit dffd5661 authored by Jiri Pirko's avatar Jiri Pirko Committed by Jakub Kicinski
Browse files

mlxsw: spectrum: Set KVH XLT cache mode for Spectrum2/3 



Set a profile option to instruct FW to use 1/2 of KVH for XLT cache, not
the whole one.

Signed-off-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 2dfad87a

drivers/net/ethernet/mellanox/mlxsw/cmd.h

+13 −0
Original line number Diff line number Diff line
@@ -674,6 +674,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); 
 */

MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1);



/* cmd_mbox_config_set_kvh_xlt_cache_mode

 * Capability bit. Setting a bit to 1 configures the profile

 * according to the mailbox contents.

 */

MLXSW_ITEM32(cmd_mbox, config_profile, set_kvh_xlt_cache_mode, 0x08, 3, 1);



/* cmd_mbox_config_profile_max_vepa_channels

 * Maximum number of VEPA channels per port (0 through 16)

 * 0 - multi-channel VEPA is disabled
@@ -800,6 +806,13 @@ MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 
 */

MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1);



/* cmd_mbox_config_profile_kvh_xlt_cache_mode

 * KVH XLT cache mode:

 * 0 - XLT can use all KVH as best-effort

 * 1 - XLT cache uses 1/2 KVH

 */

MLXSW_ITEM32(cmd_mbox, config_profile, kvh_xlt_cache_mode, 0x50, 8, 4);



/* cmd_mbox_config_kvd_linear_size

 * KVD Linear Size

 * Valid for Spectrum only

drivers/net/ethernet/mellanox/mlxsw/core.h

+3 −1
Original line number Diff line number Diff line
@@ -256,7 +256,8 @@ struct mlxsw_config_profile { 
		used_max_pkey:1,

		used_ar_sec:1,

		used_adaptive_routing_group_cap:1,

		used_kvd_sizes:1;

		used_kvd_sizes:1,

		used_kvh_xlt_cache_mode:1;

	u8	max_vepa_channels;

	u16	max_mid;

	u16	max_pgt;
@@ -278,6 +279,7 @@ struct mlxsw_config_profile { 
	u32	kvd_linear_size;

	u8	kvd_hash_single_parts;

	u8	kvd_hash_double_parts;

	u8	kvh_xlt_cache_mode;

	struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];

};

drivers/net/ethernet/mellanox/mlxsw/pci.c

+6 −0
Original line number Diff line number Diff line
@@ -1196,6 +1196,12 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 
		mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,

					MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));

	}

	if (profile->used_kvh_xlt_cache_mode) {

		mlxsw_cmd_mbox_config_profile_set_kvh_xlt_cache_mode_set(

			mbox, 1);

		mlxsw_cmd_mbox_config_profile_kvh_xlt_cache_mode_set(

			mbox, profile->kvh_xlt_cache_mode);

	}



	for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)

		mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+2 −0
Original line number Diff line number Diff line
@@ -2936,6 +2936,8 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 
	.max_ib_mc			= 0,

	.used_max_pkey			= 1,

	.max_pkey			= 0,

	.used_kvh_xlt_cache_mode	= 1,

	.kvh_xlt_cache_mode		= 1,

	.swid_config			= {

		{

			.used_type	= 1,