Commit dfcbbd73 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-renesas', 'clk-spreadtrum', 'clk-imx' and 'clk-qcom' into clk-next

* clk-renesas: (22 commits)
  clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config
  clk: renesas: r9a07g043: Add support for RZ/Five SoC
  dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
  clk: renesas: r8a779f0: Add HSCIF clocks
  clk: renesas: r8a779f0: Add PCIe clocks
  clk: renesas: r8a779f0: Add Z0 and Z1 clock support
  dt-bindings: clock: renesas,rzg2l: Simplify header file references
  clk: renesas: rza1: Remove struct rz_cpg
  clk: renesas: r8a7779: Remove struct r8a7779_cpg
  clk: renesas: r8a7778: Remove struct r8a7778_cpg
  clk: renesas: sh73a0: Remove sh73a0_cpg.reg
  clk: renesas: r8a7740: Remove r8a7740_cpg.reg
  clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
  clk: renesas: r8a779f0: Add SDHI0 clock
  clk: renesas: r8a779f0: Add thermal clock
  clk: renesas: rzg2l: Fix reset status function
  clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  clk: renesas: r9a06g032: Drop some unused fields
  clk: renesas: r9a09g011: Add WDT clock and reset entries
  clk: renesas: r9a09g011: Add PFC clock and reset entries
  ...

* clk-spreadtrum:
  clk: sprd: Add dt-bindings include file for UMS512
  dt-bindings: clk: sprd: Add bindings for ums512 clock controller

* clk-imx:
  clk: imx: clk-fracn-gppll: Add more freq config for video pll
  clk: imx: clk-fracn-gppll: correct rdiv
  clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()
  clk: imx: clk-fracn-gppll: fix mfd value
  clk: imx93: Correct the edma1's parent clock
  clk: imx93: correct nic_media parent
  clk: imx93: use adc_root as the parent clock of adc1

* clk-qcom: (62 commits)
  clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
  clk: qcom: clk-rpm: convert to parent_data API
  dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
  clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
  clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
  clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
  clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
  clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
  clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
  clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
  clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
  clk: qcom: fix build error initializer element is not constant
  dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
  clk: qcom: add support for SM8350 DISPCC
  clk: qcom: add support for SM8350 GPUCC
  clk: qcom: add camera clock controller driver for SM8450 SoC
  clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces
  clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces
  clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code
  clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description
  ...
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+4 −2
Original line number Diff line number Diff line
@@ -4,18 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains on SM8150 and SM8250.
  power domains on SM8150/SM8250/SM8350.

  See also:
    dt-bindings/clock/qcom,dispcc-sm8150.h
    dt-bindings/clock/qcom,dispcc-sm8250.h
    dt-bindings/clock/qcom,dispcc-sm8350.h

properties:
  compatible:
@@ -23,6 +24,7 @@ properties:
      - qcom,sc8180x-dispcc
      - qcom,sm8150-dispcc
      - qcom,sm8250-dispcc
      - qcom,sm8350-dispcc

  clocks:
    items:
+31 −9
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960

allOf:
  - $ref: qcom,gcc.yaml#
@@ -23,11 +23,25 @@ description: |

properties:
  compatible:
    const: qcom,gcc-apq8064
    oneOf:
      - items:
          - enum:
              - qcom,gcc-apq8064
              - qcom,gcc-msm8960
          - const: syscon
      - enum:
          - qcom,gcc-apq8064
          - qcom,gcc-msm8960
        deprecated: true

  thermal-sensor:
    description: child tsens device
    $ref: /schemas/thermal/qcom-tsens.yaml#

  nvmem-cells:
    minItems: 1
    maxItems: 2
    deprecated: true
    description:
      Qualcomm TSENS (thermal sensor device) on some devices can
      be part of GCC and hence the TSENS properties can also be part
@@ -37,31 +51,39 @@ properties:

  nvmem-cell-names:
    minItems: 1
    deprecated: true
    items:
      - const: calib
      - const: calib_backup

  '#thermal-sensor-cells':
    const: 1
    deprecated: true

required:
  - compatible
  - nvmem-cells
  - nvmem-cell-names
  - '#thermal-sensor-cells'

unevaluatedProperties: false

examples:
  - |
    clock-controller@900000 {
      compatible = "qcom,gcc-apq8064";
      compatible = "qcom,gcc-apq8064", "syscon";
      reg = <0x00900000 0x4000>;
      nvmem-cells = <&tsens_calib>, <&tsens_backup>;
      nvmem-cell-names = "calib", "calib_backup";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;

      thermal-sensor {
        compatible = "qcom,msm8960-tsens";

        nvmem-cells = <&tsens_calib>, <&tsens_backup>;
        nvmem-cell-names = "calib", "calib_backup";
        interrupts = <0 178 4>;
        interrupt-names = "uplow";

        #qcom,sensors = <11>;
        #thermal-sensor-cells = <1>;
      };
    };
...
+5 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ properties:
  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  '#reset-cells':
    const: 1

@@ -38,6 +41,7 @@ required:
  - compatible
  - reg
  - '#clock-cells'
  - '#power-domain-cells'
  - '#reset-cells'

additionalProperties: false
@@ -48,6 +52,7 @@ examples:
      compatible = "qcom,gcc-ipq8074";
      reg = <0x01800000 0x80000>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
      #reset-cells = <1>;
    };
...
+16 −0
Original line number Diff line number Diff line
@@ -22,16 +22,32 @@ properties:
    const: qcom,gcc-msm8996

  clocks:
    minItems: 3
    items:
      - description: XO source
      - description: Second XO source
      - description: Sleep clock source
      - description: PCIe 0 PIPE clock (optional)
      - description: PCIe 1 PIPE clock (optional)
      - description: PCIe 2 PIPE clock (optional)
      - description: USB3 PIPE clock (optional)
      - description: UFS RX symbol 0 clock (optional)
      - description: UFS RX symbol 1 clock (optional)
      - description: UFS TX symbol 0 clock (optional)

  clock-names:
    minItems: 3
    items:
      - const: cxo
      - const: cxo2
      - const: sleep_clk
      - const: pcie_0_pipe_clk_src
      - const: pcie_1_pipe_clk_src
      - const: pcie_2_pipe_clk_src
      - const: usb3_phy_pipe_clk_src
      - const: ufs_rx_symbol_0_clk_src
      - const: ufs_rx_symbol_1_clk_src
      - const: ufs_tx_symbol_0_clk_src

  '#clock-cells':
    const: 1
+2 −3
Original line number Diff line number Diff line
@@ -44,7 +44,6 @@ properties:
      - qcom,gcc-msm8916
      - qcom,gcc-msm8939
      - qcom,gcc-msm8953
      - qcom,gcc-msm8960
      - qcom,gcc-msm8974
      - qcom,gcc-msm8974pro
      - qcom,gcc-msm8974pro-ac
@@ -58,10 +57,10 @@ required:
unevaluatedProperties: false

examples:
  # Example for GCC for MSM8960:
  # Example for GCC for MSM8974:
  - |
    clock-controller@900000 {
      compatible = "qcom,gcc-msm8960";
      compatible = "qcom,gcc-msm8974";
      reg = <0x900000 0x4000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
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