Commit df2c2e70 authored by Imre Deak's avatar Imre Deak Committed by Tony Lindgren
Browse files

ARM: OMAP: add SoSSI clock 



This is needed, so that disabling the SoSSI clock during idle can
be prevented.

Signed-off-by: default avatarImre Deak <imre.deak@solidboot.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent c72d8950

arch/arm/mach-omap1/clock.c

+34 −0
Original line number Diff line number Diff line
@@ -49,6 +49,15 @@ static void omap1_uart_recalc(struct clk * clk) 
		clk->rate = 12000000;

}



static void omap1_sossi_recalc(struct clk *clk)

{

	u32 div = omap_readl(MOD_CONF_CTRL_1);



	div = (div >> 17) & 0x7;

	div++;

	clk->rate = clk->parent->rate / div;

}



static int omap1_clk_enable_dsp_domain(struct clk *clk)

{

	int retval;
@@ -396,6 +405,31 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 
	return 0;

}



static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)

{

	u32 l;

	int div;

	unsigned long p_rate;



	p_rate = clk->parent->rate;

	/* Round towards slower frequency */

	div = (p_rate + rate - 1) / rate;

	div--;

	if (div < 0 || div > 7)

		return -EINVAL;



	l = omap_readl(MOD_CONF_CTRL_1);

	l &= ~(7 << 17);

	l |= div << 17;

	omap_writel(l, MOD_CONF_CTRL_1);



	clk->rate = p_rate / (div + 1);

	if (unlikely(clk->flags & RATE_PROPAGATES))

		propagate_rate(clk);



	return 0;

}



static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)

{

	return 96000000 / calc_ext_dsor(rate);

arch/arm/mach-omap1/clock.h

+19 −2
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk); 
static void omap1_clk_disable_generic(struct clk * clk);

static void omap1_ckctl_recalc(struct clk * clk);

static void omap1_watchdog_recalc(struct clk * clk);

static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);

static void omap1_sossi_recalc(struct clk *clk);

static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);

static int omap1_clk_enable_dsp_domain(struct clk * clk);

static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
@@ -170,7 +172,8 @@ static struct arm_idlect1_clk ck_dpll1out = { 
	.clk = {

		.name		= "ck_dpll1out",

		.parent		= &ck_dpll1,

		.flags		= CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,

		.flags		= CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |

				  ENABLE_REG_32BIT | RATE_PROPAGATES,

		.enable_reg	= (void __iomem *)ARM_IDLECT2,

		.enable_bit	= EN_CKOUT_ARM,

		.recalc		= &followparent_recalc,
@@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = { 
	.idlect_shift	= 12,

};



static struct clk sossi_ck = {

	.name		= "ck_sossi",

	.parent		= &ck_dpll1out.clk,

	.flags		= CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |

			  ENABLE_REG_32BIT,

	.enable_reg	= (void __iomem *)MOD_CONF_CTRL_1,

	.enable_bit	= 16,

	.recalc		= &omap1_sossi_recalc,

	.set_rate	= &omap1_set_sossi_rate,

	.enable		= &omap1_clk_enable_generic,

	.disable	= &omap1_clk_disable_generic,

};



static struct clk arm_ck = {

	.name		= "arm_ck",

	.parent		= &ck_dpll1,
@@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = { 
	&ck_dpll1,

	/* CK_GEN1 clocks */

	&ck_dpll1out.clk,

	&sossi_ck,

	&arm_ck,

	&armper_ck.clk,

	&arm_gpio_ck,