Commit df1e4706 authored by Hui Tang's avatar Hui Tang Committed by Zheng Zengkai
Browse files

crypto: hisilicon/hpre - delete ECC 1bit error reported threshold 

mainline inclusion
from mainline-v5.12-rc1-dontuse
commit 09228c03
category: bugfix
bugzilla: 173981
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=09228c03775447a6e3b30e06abd3219f79bb32a1



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Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre,
since register 'QM_RAS_CE_THRESHOLD' of qm has done this work.

Signed-off-by: default avatarHui Tang <tanghui20@huawei.com>
Reviewed-by: default avatarZaibo Xu <xuzaibo@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: default avatarMingqiang Ling <lingmingqiang@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 9033a373

drivers/crypto/hisilicon/hpre/hpre_main.c

+0 −2
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 
#define HPRE_INT_STATUS			0x301800

#define HPRE_CORE_INT_ENABLE		0

#define HPRE_CORE_INT_DISABLE		0x003fffff

#define HPRE_RAS_ECC_1BIT_TH		0x30140c

#define HPRE_RDCHN_INI_ST		0x301a00

#define HPRE_CLSTR_BASE			0x302000

#define HPRE_CORE_EN_OFFSET		0x04
@@ -312,7 +311,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) 
	writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE));

	writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN));

	writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK));

	writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH));

	writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS));

	writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE));

	writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS));