Commit df16b636 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Lucas De Marchi
Browse files

drm/i915/tgl: select correct bit for port select 



Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.

v2 (Lucas):
  - Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
    {TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
  - Also cover haswell_get_ddi_port_state() in intel_display.c that was
    missing
  - Define macros using the _SHIFT macros so we don't lose other users

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3-lucas.demarchi@intel.com
parent 98a5c2a3

drivers/gpu/drm/i915/display/intel_ddi.c

+37 −10
Original line number Diff line number Diff line
@@ -1773,6 +1773,9 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) 


	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */

	temp = TRANS_DDI_FUNC_ENABLE;

	if (INTEL_GEN(dev_priv) >= 12)

		temp |= TGL_TRANS_DDI_SELECT_PORT(port);

	else

		temp |= TRANS_DDI_SELECT_PORT(port);



	switch (crtc_state->pipe_bpp) {
@@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state 
	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);

	u32 val = I915_READ(reg);



	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);

	val |= TRANS_DDI_PORT_NONE;

	if (INTEL_GEN(dev_priv) >= 12) {

		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |

			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);

	} else {

		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |

			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);

	}

	I915_WRITE(reg, val);



	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2006,10 +2014,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 
	mst_pipe_mask = 0;

	for_each_pipe(dev_priv, p) {

		enum transcoder cpu_transcoder = (enum transcoder)p;

		unsigned int port_mask, ddi_select;



		if (INTEL_GEN(dev_priv) >= 12) {

			port_mask = TGL_TRANS_DDI_PORT_MASK;

			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);

		} else {

			port_mask = TRANS_DDI_PORT_MASK;

			ddi_select = TRANS_DDI_SELECT_PORT(port);

		}



		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));



		if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))

		if ((tmp & port_mask) != ddi_select)

			continue;



		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2126,20 +2143,30 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) 
	enum port port = encoder->port;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;



	if (cpu_transcoder != TRANSCODER_EDP)

	if (cpu_transcoder != TRANSCODER_EDP) {

		if (INTEL_GEN(dev_priv) >= 12)

			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),

				   TGL_TRANS_CLK_SEL_PORT(port));

		else

			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),

				   TRANS_CLK_SEL_PORT(port));

	}

}



void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;



	if (cpu_transcoder != TRANSCODER_EDP)

	if (cpu_transcoder != TRANSCODER_EDP) {

		if (INTEL_GEN(dev_priv) >= 12)

			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),

				   TGL_TRANS_CLK_SEL_DISABLED);

		else

			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),

				   TRANS_CLK_SEL_DISABLED);

	}

}



static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,

				enum port port, u8 iboost)

drivers/gpu/drm/i915/display/intel_display.c

+5 −1
Original line number Diff line number Diff line
@@ -10353,6 +10353,10 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 


	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));



	if (INTEL_GEN(dev_priv) >= 12)

		port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>

			TGL_TRANS_DDI_PORT_SHIFT;

	else

		port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;



	if (INTEL_GEN(dev_priv) >= 11)

drivers/gpu/drm/i915/i915_reg.h

+8 −3
Original line number Diff line number Diff line
@@ -9384,10 +9384,12 @@ enum skl_power_gate { 


#define  TRANS_DDI_FUNC_ENABLE		(1 << 31)

/* Those bits are ignored by pipe EDP since it can only connect to DDI A */

#define  TRANS_DDI_PORT_MASK		(7 << 28)

#define  TRANS_DDI_PORT_SHIFT		28

#define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)

#define  TRANS_DDI_PORT_NONE		(0 << 28)

#define  TGL_TRANS_DDI_PORT_SHIFT	27

#define  TRANS_DDI_PORT_MASK		(7 << TRANS_DDI_PORT_SHIFT)

#define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)

#define  TRANS_DDI_SELECT_PORT(x)	((x) << TRANS_DDI_PORT_SHIFT)

#define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)

#define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)

#define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)

#define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
@@ -9597,6 +9599,9 @@ enum skl_power_gate { 
/* For each transcoder, we need to select the corresponding port clock */

#define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)

#define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)

#define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)

#define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)





#define CDCLK_FREQ			_MMIO(0x46200)