Commit defbbcd9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.15-2021-10-21' of... 

Merge tag 'amd-drm-fixes-5.15-2021-10-21' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.15-2021-10-21:

amdgpu:
- Fix a potential out of bounds write in debugfs
- Fix revision handling for Yellow Carp
- Display fixes for Yellow Carp

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211021203430.4578-1-alexander.deucher@amd.com
parents 3906fe9b 53c2ff8b

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −1
Original line number Diff line number Diff line
@@ -1257,7 +1257,7 @@ static int nv_common_early_init(void *handle) 
			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG;

		if (adev->pdev->device == 0x1681)

			adev->external_rev_id = adev->rev_id + 0x19;

			adev->external_rev_id = 0x20;

		else

			adev->external_rev_id = adev->rev_id + 0x01;

		break;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 
	if (!wr_buf)

		return -ENOSPC;



	if (parse_write_buffer_into_params(wr_buf, size,

	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,

					   (long *)param, buf,

					   max_param_num,

					   &param_nums)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+8 −8
Original line number Diff line number Diff line
@@ -366,32 +366,32 @@ static struct wm_table lpddr5_wm_table = { 
			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 5.32,

			.sr_enter_plus_exit_time_us = 6.38,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.82,

			.sr_enter_plus_exit_time_us = 11.196,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.89,

			.sr_enter_plus_exit_time_us = 11.24,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 9.748,

			.sr_enter_plus_exit_time_us = 11.102,

			.sr_exit_time_us = 11.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

		},

	}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+3 −4
Original line number Diff line number Diff line
@@ -76,10 +76,6 @@ void dcn31_init_hw(struct dc *dc) 
	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)

		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);



	// Initialize the dccg

	if (res_pool->dccg->funcs->dccg_init)

		res_pool->dccg->funcs->dccg_init(res_pool->dccg);



	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {



		REG_WRITE(REFCLK_CNTL, 0);
@@ -106,6 +102,9 @@ void dcn31_init_hw(struct dc *dc) 
		hws->funcs.bios_golden_init(dc);

		hws->funcs.disable_vga(dc->hwseq);

	}

	// Initialize the dccg

	if (res_pool->dccg->funcs->dccg_init)

		res_pool->dccg->funcs->dccg_init(res_pool->dccg);



	if (dc->debug.enable_mem_low_power.bits.dmcu) {

		// Force ERAM to shutdown if DMCU is not enabled

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+10 −3
Original line number Diff line number Diff line
@@ -217,8 +217,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = { 
	.num_states = 5,

	.sr_exit_time_us = 9.0,

	.sr_enter_plus_exit_time_us = 11.0,

	.sr_exit_z8_time_us = 402.0,

	.sr_enter_plus_exit_z8_time_us = 520.0,

	.sr_exit_z8_time_us = 442.0,

	.sr_enter_plus_exit_z8_time_us = 560.0,

	.writeback_latency_us = 12.0,

	.dram_channel_width_bytes = 4,

	.round_trip_ping_latency_dcfclk_cycles = 106,
@@ -928,7 +928,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
	.disable_dcc = DCC_ENABLE,

	.vsr_support = true,

	.performance_trace = false,

	.max_downscale_src_width = 3840,/*upto 4K*/

	.max_downscale_src_width = 4096,/*upto true 4K*/

	.disable_pplib_wm_range = false,

	.scl_reset_length10 = true,

	.sanity_checks = false,
@@ -1590,6 +1590,13 @@ static int dcn31_populate_dml_pipes_from_context( 
		pipe = &res_ctx->pipe_ctx[i];

		timing = &pipe->stream->timing;



		/*

		 * Immediate flip can be set dynamically after enabling the plane.

		 * We need to require support for immediate flip or underflow can be

		 * intermittently experienced depending on peak b/w requirements.

		 */

		pipes[pipe_cnt].pipe.src.immediate_flip = true;



		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;

		pipes[pipe_cnt].pipe.src.gpuvm = true;

		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;