Commit ded091fe authored by Linus Walleij's avatar Linus Walleij Committed by Vinod Koul
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dmaengine: pl08x: Use the BIT() macro consistently 



This makes the driver shift bits with BIT() which is used on other
places in the driver.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent da7cbd20

drivers/dma/amba-pl08x.c

+5 −5
Original line number Diff line number Diff line
@@ -420,7 +420,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan) 


	/* Enable the DMA channel */

	/* Do not access config register until channel shows as disabled */

	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))

	while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))

		cpu_relax();



	/* Do not access config register until channel shows as inactive */
@@ -487,8 +487,8 @@ static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, 


	writel(val, ch->reg_config);



	writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);

	writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);

	writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);

	writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);

}



static inline u32 get_bytes_in_cctl(u32 cctl)
@@ -1837,7 +1837,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev) 
		return IRQ_NONE;



	for (i = 0; i < pl08x->vd->channels; i++) {

		if (((1 << i) & err) || ((1 << i) & tc)) {

		if ((BIT(i) & err) || (BIT(i) & tc)) {

			/* Locate physical channel */

			struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];

			struct pl08x_dma_chan *plchan = phychan->serving;
@@ -1875,7 +1875,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev) 
			}

			spin_unlock(&plchan->vc.lock);



			mask |= (1 << i);

			mask |= BIT(i);

		}

	}

include/linux/amba/pl080.h

+20 −20
Original line number Diff line number Diff line
@@ -38,9 +38,9 @@ 
#define PL080_SOFT_LSREQ			(0x2C)



#define PL080_CONFIG				(0x30)

#define PL080_CONFIG_M2_BE			(1 << 2)

#define PL080_CONFIG_M1_BE			(1 << 1)

#define PL080_CONFIG_ENABLE			(1 << 0)

#define PL080_CONFIG_M2_BE			BIT(2)

#define PL080_CONFIG_M1_BE			BIT(1)

#define PL080_CONFIG_ENABLE			BIT(0)



#define PL080_SYNC				(0x34)
@@ -58,18 +58,18 @@ 


#define PL080_LLI_ADDR_MASK			(0x3fffffff << 2)

#define PL080_LLI_ADDR_SHIFT			(2)

#define PL080_LLI_LM_AHB2			(1 << 0)

#define PL080_LLI_LM_AHB2			BIT(0)



#define PL080_CONTROL_TC_IRQ_EN			(1 << 31)

#define PL080_CONTROL_TC_IRQ_EN			BIT(31)

#define PL080_CONTROL_PROT_MASK			(0x7 << 28)

#define PL080_CONTROL_PROT_SHIFT		(28)

#define PL080_CONTROL_PROT_CACHE		(1 << 30)

#define PL080_CONTROL_PROT_BUFF			(1 << 29)

#define PL080_CONTROL_PROT_SYS			(1 << 28)

#define PL080_CONTROL_DST_INCR			(1 << 27)

#define PL080_CONTROL_SRC_INCR			(1 << 26)

#define PL080_CONTROL_DST_AHB2			(1 << 25)

#define PL080_CONTROL_SRC_AHB2			(1 << 24)

#define PL080_CONTROL_PROT_CACHE		BIT(30)

#define PL080_CONTROL_PROT_BUFF			BIT(29)

#define PL080_CONTROL_PROT_SYS			BIT(28)

#define PL080_CONTROL_DST_INCR			BIT(27)

#define PL080_CONTROL_SRC_INCR			BIT(26)

#define PL080_CONTROL_DST_AHB2			BIT(25)

#define PL080_CONTROL_SRC_AHB2			BIT(24)

#define PL080_CONTROL_DWIDTH_MASK		(0x7 << 21)

#define PL080_CONTROL_DWIDTH_SHIFT		(21)

#define PL080_CONTROL_SWIDTH_MASK		(0x7 << 18)
@@ -95,20 +95,20 @@ 
#define PL080_WIDTH_16BIT			(0x1)

#define PL080_WIDTH_32BIT			(0x2)



#define PL080N_CONFIG_ITPROT			(1 << 20)

#define PL080N_CONFIG_SECPROT			(1 << 19)

#define PL080_CONFIG_HALT			(1 << 18)

#define PL080_CONFIG_ACTIVE			(1 << 17)  /* RO */

#define PL080_CONFIG_LOCK			(1 << 16)

#define PL080_CONFIG_TC_IRQ_MASK		(1 << 15)

#define PL080_CONFIG_ERR_IRQ_MASK		(1 << 14)

#define PL080N_CONFIG_ITPROT			BIT(20)

#define PL080N_CONFIG_SECPROT			BIT(19)

#define PL080_CONFIG_HALT			BIT(18)

#define PL080_CONFIG_ACTIVE			BIT(17)  /* RO */

#define PL080_CONFIG_LOCK			BIT(16)

#define PL080_CONFIG_TC_IRQ_MASK		BIT(15)

#define PL080_CONFIG_ERR_IRQ_MASK		BIT(14)

#define PL080_CONFIG_FLOW_CONTROL_MASK		(0x7 << 11)

#define PL080_CONFIG_FLOW_CONTROL_SHIFT		(11)

#define PL080_CONFIG_DST_SEL_MASK		(0xf << 6)

#define PL080_CONFIG_DST_SEL_SHIFT		(6)

#define PL080_CONFIG_SRC_SEL_MASK		(0xf << 1)

#define PL080_CONFIG_SRC_SEL_SHIFT		(1)

#define PL080_CONFIG_ENABLE			(1 << 0)

#define PL080_CONFIG_ENABLE			BIT(0)



#define PL080_FLOW_MEM2MEM			(0x0)

#define PL080_FLOW_MEM2PER			(0x1)